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Title Electrical Performance Depending on the Grain Boundary-location in the Multiple Nanosheet Tunneling Field-effect Transistor based on the Poly-Si
Authors (Ga Eon Kang) ; (Sang Ho Lee) ; (Jin Park) ; (So Ra Min) ; (Geon Uk Kim) ; (Jun Hyeok Heo) ; (Jaewon Jang) ; (Jin-Hyuk Bae) ; (Sin-Hyung Lee) ; (In Man Kang)
Page pp.8-16
ISSN 1598-1657
Keywords Multiple nanosheet tunneling field-effect transistor (MNSTFET); polycrystalline silicon (Poly-Si); grain boundary (GB)
Abstract In this study, we present the electrical characteristics of the multiple nanosheet tunneling field-effect transistors (MNSTFETs) based on the polycrystalline silicon (poly-Si) depending on the grain boundary (GB)-locations. The effects of the GB are analyzed for 5 locations and they are compared with the device without the GB. When the GB was located in the tunneling region, the electrical performances were the most inferior compared with the device without the GB. In addition, it shows the electrical characteristics of 125 samples of the MNSTFETs compared with the multiple nanosheet metal-oxide-semiconductor field-effect transistors (MNSMOSFETs). The standard deviations (SDs) of the threshold voltage (VT) of MNSTFET and MNSMOSFET are 3.90 mV and 8.31 mV, respectively. If the GB is not located at 24 nm, the SDs of the average of subthreshold swing (SSave) are 1.50 mV/dec and 4.16 mV/dec, respectively. This simulation shows that the MNSTFET has smaller effect depending on the GB location than the MNSMOSFET.