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REFERENCES

1 
Roshan-Zamir A., Elhadidy O., Yang H., Palermo S., Sept. 2017, A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS, Solid-State Circuits, IEEE Journal of, Vol. 52, No. 4, pp. 2430-2447DOI
2 
Im J., Dec 2017, A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET, Solid-State Circuits, IEEE Journal of, Vol. 52, No. 12, pp. 3486-3502DOI
3 
Payne R., Dec 2005, A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels, Solid-State Circuits, IEEE Journal of, Vol. 40, No. 12, pp. 2646-2657DOI
4 
Roshan-Zamir A., Mar 2019, A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS, Solid-State Circuits, IEEE Journal of, Vol. 54, No. 3, pp. 672-684DOI
5 
Dolan M., Yuan F., MA. 2017, An adaptive edge decision feedback equalizer with 4PAM signaling, Circuit and Systems, 2017, MWSCAS 2017, 60th IEEE International Midwest Symposium on, pp. 535-538DOI
6 
Fei YUAN, 2014, Design techniques for decision feedback equalization of multi-giga-bit-per-second serial data links: a state-of-the-art review, Devices & Systems, 2014, IET Circuits, Vol. 8, pp. 118-130DOI
7 
Chen K., Chen W., Liu S., Nov 2017, A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS, Circuits and Systems II : IEEE Transactions on, Vol. 64, No. 11, pp. 1282-1286DOI
8 
Krupnik Y., IEEE Journal of, 112-Gb/s PAM4 ADC-Based SERDES Receiver with Resonant AFE for Long-Reach Channels, Solid-State Circuits, IEEE Journal of, Vol. 55, No. 4, pp. 1077-1085DOI
9 
Li Y., Yuan F., MA. 2017, Adaptive data-transition decision feedback equalizer for serial links, Circuit and Systems, 2017, MWSCAS 2017, 60th IEEE International Midwest Symposium on, pp. 1609-1612DOI
10 
Chen K. -C., Kuo W. W. -T., Emami A., Mar 2021, A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS, Solid-State Circuits, IEEE Journal of, Vol. 56, No. 3, pp. 750-762DOI
11 
Jung J. W., Razavi B., Feb 2015, A 25 Gb/s 5.8 mW CMOS Equalizer, Solid-State Circuits, IEEE Journal of, Vol. 50, No. 2, pp. 515-526DOI
12 
LEE J., Chiang P., Peng P., Chen L., Weng C., Sep 2015, Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies, Solid-State Circuits, IEEE Journal of, Vol. 50, No. 9, pp. 2061-2073DOI