1. Direct DFE and Speculative DFE

Fig. 1(a) shows a one tap direct DFE and Fig. 1(b) shows a one tap speculative DFE on a PAM-4 full data rate case for clarity. In the direct DFE structure, the time constraint of the critical path is given as

where $\mathrm{T}_{\mathrm{clk}-\mathrm{q}}$ is the clock-to-q delay of sampler, + $\mathrm{T}_{ ext {prop-vtoi }}$ is the propagation delay from the change in digitized $h1$ value to the change the current of the summer, and $\mathrm{T}_{ ext {sum-settle }}$ is settling time of summer output voltage in response to the summer current change. There is a speculative structure as a way to relax the time constraint in the direct DFE. The speculative structure does not require the settling time because ISI is not removed from the output node of the summer. However, the output nodes of summer need to drive 4x more samplers compared to the direct DFE. In other words, when multiplexers and encoders are included, 4 times more hardware is required than the direct DFE. Moreover, the loop created by the multiplexers to select a reliable value diminishes the advantage of speculative structure ⁽²⁾. In the speculative DFE structure, the time constraint of the critical path is given as

where $\mathrm{T}_{\text {prop-mux }}$ is mux propagation delay. Since there are no feedback equalization actions through the summer, $\mathrm{T}_{ ext {prop-vtoi }}$ and $\mathrm{T}_{ ext {sum-settle }}$ are removed and only $\mathrm{T}_{\text {prop-mux }}$ is added. Therefore, it is easier for the speculative DFE to satisfy time constraint than direct structure.

2. Proposed DFE with Extended Time Constraint

A non-speculative adaptive DFE structure with a 1.5UI timing constraint is proposed. The proposed approach minimizes additional hardware while overcoming the drawbacks in direct DFE and speculative DFE. Fig. 2 shows a block diagram of proposed DFE for quarter-rate PAM-4 signaling. Compared to the conventional DFE structures, two samplers (DFE sampler and DATA sampler) were used. In preceding stage, a CTLE is employed to boost the high frequency components of the input signal. The output of CTLE needs to be tracked and held and a bootstrap structure of the track and hold (T&H) circuit is adopted in this work ^(1,8). T&H tracks output of CTLE for 2 UI on the falling edge of the clock and holds it for 2 UI on the rising edge of the clock. The output of T&H is equalized once again by DFE and then sampled by two types of samplers in different phases of clock. In direct DFE structure, only output of the data sampler is used as a tap coefficient, and it is encoded and used as recovered data. In proposed approach the role of DFE sampler and DATA sampler is different as described below. The output of the DFE sampler is used as a coefficient of tap and the output of the DATA sampler is encoded and used as data. A detailed timing diagram of the sampler is shown in Fig. 3. One T&H circuit tracks the input signal for 2UI from the falling edge of CLK270 and holds it for 2UI from the rising edge of CLK270. The output of this track and hold is shown as EYE270 in Fig. 3. EYE270 is sampled by the DFE sampler on the rising edge of CLK0 and by the DATA sampler on the rising edge of CLK45, respectively. The output of the DFE sampler by sampling EYE270 at CLK0 is used as the tap coefficient for equalizing EYE0. Equalized EYE0 is sampled by the DATA sampler at CLK135 and is used as recovered data. Since EYE0 is equalized by the output of the DFE sampler sampled at CLK0, it has 1.5UI timing margin from CLK0 to CLK135 for equalization. Therefore, 1UI time constraint of direct DFE can be extended to 1.5UI by separating the roles that one sampler was performing into DFE sampler and DATA sampler with different sampling timing. Eq. (3) represents the timing constraint of critical path from DFE sampler to DATA sampler, and Eq. (4) represents the timing constraint of critical path between two DFE samplers.

In order for the output voltage of summer is properly converged, the coefficient of tap must be completed within 0.5UI ⁽³⁾. Considering the case where equalization by tap has enough settling time, the time margin except the settling time is 0.5UI for the direct DFE and 1UI for the proposed DFE. Thus, the proposed DFE structure can take care of 2 times higher speed of data with enough settling time.

Table 1 and 2 show the values obtained by simulation of feedback delays for several data rates using a 65nm CMOS process when using strong-arm type latches and current mode logic (CML) type latches, respectively. Fig. 4 and 5 show the schematic of the strong-arm latch and CML-latch used to obtain the feedback delay ^(6,11). Table 1 shows that delay margin of the proposed DFE structure for 10 Gb/s input data is the same as that of 5 Gb/s in direct DFE structure. When using the strong-arm latch case, the direct DFE has an enough settling time up to 5 Gb/s data rate, while the proposed DFE structure can have an enough settling time up to 10 Gb/s data rate. In the case of the CML latch as shown in Table 2, input data rate with an enough settling time goes up from 15 Gb/s to 30 Gb/s. In the case of 7.5 Gb/s input data in Table 1, the 1UI time constraint has a negative delay margin of -0.16UI. That is, when the first tap with a direct DFE structure is implemented, it has a tap coefficient by the preceding data but always has insufficient settling time. Signals equalized by insufficient settling time have a relatively high probability of incorrect sampling output. This not only causes a bit error, but also causes an erroneous tap coefficient. In the case of the proposed 1.5UI structure, the delay margin is 0.34UI, which is sufficient for the settling time. That is, the signal equalized by the output of the DFE sampler is sampled by the DATA sampler with sufficient settling time. The DFE sampler has a time constraint of 1 UI, so it has insufficient settling time. Even if an error occurs in the output of the DFE sampler due to insufficient settling time, since the DATA sampler has sufficient settling time, a bit error does not occur. However, a problem occurs in the tap coefficient for the next sample. The output of the DATA sampler is more reliable than that of the DFE sampler because it has sufficient settling time. So, if an error occurs at the output of the DFE sampler, it is desirable to adjust the tap coefficient through the output of the DATA sampler. If the DFE sampler and the DATA sampler have the same value, the tap coefficient will have the correct value in advance by 0.5UI. And, if the DFE sampler and the DATA sampler have different outputs, i.e., if the output of the DFE sampler has an error, the tap coefficient is modified by the DATA sampler, so tap coefficient always has the correct value. That is, at 7.5 Gb/s signal, the direct DFE structure generate a bit error and tap coefficient error when the output of sampler is wrong. However, the proposed DFE structure, bit error does not occur because the DATA sampler has enough settling time. Also, because the tap coefficient is modified by the output of the DATA sampler when an error occurs in the output of DFE sampler, tap coefficient has always correct value. Likewise, in the case of 22.5 Gb/s in CML latch case as Table 2, the direct DFE has an insufficient settling time with a delay margin of -0.18UI, while the proposed DFE can implement a first tap with a sufficient settling time with a delay margin of 0.32UI. In Table 3, the number of samplers of the two conventional structures and the proposed structure are compared ⁽²⁾. Too many samplers increase the load capacitance of summer, which limits of the maximum equalization frequency range and excessively increasing power consumption. In PAM-4 signaling, the speculative structure requires 4 times more samplers of all types compare to the direct structure, while the proposed structure add only the DFE sampler to obtain extended time constraint. Table 4 shows the power consumption in each of the simulated cases above. As can be seen in Table 3, the proposed DFE can minimize the number of additional samplers, thus minimizing the additional power consumption compared to the speculative DFE.

3. DFE FIR Tap and Tap Weight Adaptation Algorithm

In general, DFE taps consist of NMOS taps ^(2,4). In the NMOS only tap, the stronger the current weight, the lower the common voltage of the signal. This causes several problems. First, too low common voltage reduces the gain and adversely affects the linearity of the summer, which have a critical effect on PAM4 signal with three eyes at the same time. Second, the sampler should be designed in consideration of the region of lower common voltage. Too low common voltage can change $\mathrm{T}_{\mathrm{clk}-\mathrm{q}}$, which causes a change in feedback delay. Finally, it causes a change in the threshold voltage of the PAM4 signal. The data level and threshold voltage determined based on the signal equalized by output of CTLE have different values by NMOS tap. This would require the re-establishment of data levels and threshold voltages. These issues would require a wide range of operating regions for summer and DAC, which would result in a mismatch. Thus, by using low voltage differential signaling (LVDS) tap, it is possible to keep the common voltage of the signal constant regardless of the weight through directional equalization ⁽⁵⁾.

The circuit design of LVDS tap is given in Fig. 2. The current weight of the tap was controlled through the sign-sign least mean square (SS-LMS) algorithm. Eq. (5), C is the weight of tap, Δ is the step size of weight, $\operatorname{sign}\left[\varepsilon_{\mathrm{k}}\right]$ is the output of the error sampler, $\operatorname{sign}\left[\mathrm{V}_{\mathrm{k}-1}\right]$ is the output of the DATA sampler. The output of the DATA sampler specifies the $\operatorname{sign}\left[\varepsilon_{\mathrm{k}}\right]$ among 4 error samplers. The on and off of 3 taps is operated by the outputs of 3 DFE samplers and has the same coefficient.