Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2020-12 (Vol.20 No.06)
  4. 10.5573/JSTS.2020.20.6.558
XML PDF INFO REF

REFERENCES

1 
Sakurai T., 1993, High-speed circuit design with scaled-down MOSFET’s and low supply voltage, in Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 1487-1490DOI
2 
Yakimets D., 2018, Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology, in Technical Digest - International Electron Devices Meeting, IEDM, pp. 20.4.1-20.4.4DOI
3 
Asra R., Shrivastava M., Murali K. V. R. M., Pandey R. K., Gossner H., Rao V. R., 2011, A tunnel FET for VDD scaling below 0.6 v with a CMOS-comparable performance, IEEE Trans. Electron Devices, Vol. 58, No. 7, pp. 1855-1863DOI
4 
Gandhi R., Chen Z., Singh N., Banerjee K., Lee S., 2011, CMOS-Compatible vertical-silicon-nanowire gate-all-around P-Type tunneling FETs with ≤ 5-mV/decade subthreshold swing, IEEE Electron Device Lett., Vol. 32, No. 11, pp. 1504-1506DOI
5 
Lanuzza M., Strangio S., Crupi F., Palestri P., Esseni D., 2015, Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain, IEEE Trans. Electron Devices, Vol. 62, No. 12, pp. 3973-3979DOI
6 
Kim S. W., Sun M. C., Park E., Kim J. H., Kwon D. W., Park B. G., 2016, Improvement of current drivability in high-scalable tunnel field-effect transistors with CMOS compatible self-aligned process, Electron. Lett., Vol. 52, No. 12, pp. 1071-1072DOI
7 
Biswas A., Alper C., De Michielis L., Ionescu A. M., pp 131-132, New tunnel-FET architecture with enhanced ION and improved Miller Effect for energy efficient switching, in Device Research Conference - Conference Digest, Vol. drcDOI
8 
Jeyanthi J. E., Arunsamuel T. S., 2020, Heterojunction Tunnel Field Effect Transistors-A Detailed Review, in ICDCS 2020 - 2020 5th International Conference on Devices, Circuits and Systems, pp. 326-329DOI
9 
Singh S., Raj B., 2018, Vertical Tunnel-FET Analysis for Excessive Low Power Digital Applications, in ICSCCC 2018 - 1st International Conference on Secure Cyber Computing and Communications, pp. 192-197DOI
10 
Kim J. H., Kim S., Park B. G., 2019, Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si, IEEE Trans. Electron Devices, Vol. 66, No. 4, pp. 1656-1661DOI
11 
Kim S. W., Kim J. H., Liu T. J. K., Choi W. Y., Park B. G., 2016, Demonstration of L-Shaped Tunnel Field-Effect Transistors, IEEE Trans. Electron Devices, Vol. 63, No. 4, pp. 1774-1778DOI
12 
Choi K.-M., 2009, 32nm high K metal gate (HKMG) designs for low power applications, in 2008 International SoC Design Conference, pp. I-68-I-69DOI
13 
Lee J., 2020, Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique, Solid. State. Electron., Vol. 164DOI
14 
Betti Beneventi G., Gnani E., Gnudi A., Reggiani S., Baccarani G., 2015, Optimization of a pocketed dual-metal-gate TFET by means of TCAD simulations accounting for quantization-induced bandgap widening, IEEE Trans. Electron Devices, Vol. 62, No. 1, pp. 44-51DOI
15 
Saha R., Bhowmick B., Baishya S., 2018, Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET, Micro Nano Lett., Vol. 13, No. 7, pp. 1007-1010DOI
16 
Saha R., Bhowmick B., Baishya S., 2019, Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET, Microelectron. Eng., Vol. 214, pp. 1-4DOI
17 
Lee B. H., pp 39-41, Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8Å-12Å), in Technical Digest - International Electron Devices MeetingDOI
18 
Hou Y. T., Li M. F., Low T., Kwong D. L., 2004, Metal gate work function engineering on gate leakage of MOSFETs, IEEE Trans. Electron Devices, Vol. 51, No. 11, pp. 1783-1789DOI
19 
Wang S. J., Chen I. C., Tigelaar H. L., 1991, Effects of Poly Depletion on the Estimate of Thin Dielectric Lifetime, IEEE Electron Device Lett., Vol. 12, No. 11, pp. 617-619DOI
20 
Choi K. M., Choi W. Y., 2013, Work-function variation effects of tunneling field-effect transistors (TFETs), IEEE Electron Device Lett., Vol. 34, No. 8, pp. 942-944DOI
21 
Lee Y., Nam H., Park J. D., Shin C., 2015, Study of work-function variation for high-κ/metal-gate Ge-source tunnel field-effect transistors, IEEE Trans. Electron Devices, Vol. 62, No. 7, pp. 2143-2147DOI
22 
Saha R., Bhowmick B., Baishya S., 2019, Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET, Microelectron. Eng., Vol. 214, pp. 1-4DOI
23 
Kim G., Kim J. H., Kim J., Kim S., 2020, Analysis of work-function variation effects in a tunnel field-effect transistor depending on the device structure, Appl. Sci., Vol. 10, No. 15DOI
24 
Avci U. E., 2013, Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations, in Technical Digest - International Electron Devices Meeting, IEDM,, pp. 33.4.1-33.4.4DOI
25 
Frye A., Galyon G. T., Palmer L., 2007, Crystallographic texture and whiskers in electrodeposited tin films, IEEE Trans. Electron. Packag. Manuf., Vol. 30, No. 1, pp. 2-10DOI
26 
Dadgour H., De V., Banerjee K., pp 270-277, Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design, in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, Vol. iccad, pp. 2008DOI
27 
Kim G., Lee J., Kim J. H., Kim S., 2019, High on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling, Micromachines, Vol. 10, No. 2DOI
28 
Kwon D. W., 2017, Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters with Vertical Structures, IEEE Trans. Electron Devices, Vol. 64, No. 4, pp. 1799-1805DOI
29 
Shin S. S., Kim J. H., Kim S., May 2019, L-shaped tunnel FET with stacked gates to suppress the corner effect, Jpn. J. Appl. Phys., Vol. 58, No. SD, pp. SDDE10Google Search
30 
Kim S. W., Choi W. Y., Kim H., Sun M. C., Kim H. W., Park B. G., 2012, Investigation on hump effects of L-shaped tunneling filed-effect transistors, in 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012, pp. 1-2DOI
31 
Kim S. W., Choi W. Y., 2016, Hump Effects of Germanium/Silicon Heterojunction Tunnel Field-Effect Transistors, IEEE Trans. Electron Devices, Vol. 63, No. 6, pp. 2583-2588DOI
32 
Kim J. H., Kim S. W., Kim H. W., Park B. G., 2015, Vertical type double gate tunnelling FETs with thin tunnel barrier, Electron. Lett., Vol. 51, No. 9, pp. 718-720DOI
33 
Kim J. H., Kim S., 2020, Study on the nonlinear output characteristic of tunnel field-effect transistor, J. Semicond. Technol. Sci., Vol. 20, No. 2, pp. 159-162DOI
34 
Sentaurus Device User Guide, ver. G-2012.06, Synopsys Inc.Google Search
35 
Kane E. O., Jan 1961, Theory of tunneling, J. Appl. Phys., Vol. 32, No. 1, pp. 83-91DOI
36 
Biswas A., Dan S. S., Le Royer C., Grabinski W., Ionescu A. M., 2012, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model, Microelectron. Eng., Vol. 98, pp. 334-337DOI