I. INTRODUCTION

Recently, as the use of mobile devices increases, power dissipation in integrated circuits (ICs) has been concerned dramatically. Therefore, the reduction of supply voltage ($V_{DD}$) is essential for lowering power consumption ^(1-3). To make power reduction possible, a tunneling field-effect transistor (TFET) has been attracted by lots of researching groups due to its small subthreshold swing (S), low-level off-state current ($V_{off}$), and high complementary MOS (CMOS) compatibility ^(3-6). Especially, the TFET has lower S less than the physical limit (60 mV/dec) of the metal-oxide-semiconductor FET (MOSFET) ^(7-11). However, low on-current ($V_{on}$) has been remained as a critical issue in the TFET. In order to solve this problem, various structures and materials have been proposed to improve the low Ion. Among these attempts, the applying high-κ and metal gate (HKMG) is one of the most effective technologies ^(12-14). The HKMG stack has several advantages, including low equivalent oxide thickness (EOT), low gate leakage current, low gate resistance, and no poly depletion effect ^(15-19). Despite these advantages, the metal gate brings work function (WF) variation (WFV) in the gate due to various metal particle directions ^(15,20-23). In previous researches, most of studies have been focused on variation ranges of the MOSFET and TFET ^{(15, 20-22, 24)}. However, there has been little study of WFV effect on the operation mechanism in the MOFSET and TFET.

Fig. 1. (a) Schematic cross view of TFET and MOSFET device, (b) Top view of TFET and MOSFET. The randomized WF is applied to the gate.

This paper aim to discuss the WFV effects by drain bias in the TFET. Based on the same structure except for the doping types, it compares and analyzes how the MOSFET and TFET affect current fluctuations with the same WFV. The paper consists as follows: Section 2 describes the MOSFET/TFET structure and models used in simulation. In Section 3, the WFV effects are compared with various drain voltage ($V_{DS}$). Especially, this study is focusing on limiting factor for WFV effect according to the applied $V_{DS}$. In order to verify the cause of limiting WFV effect, the surface channel potential, charge density, and gate-to-drain capacitance ($C_{GD}$) in the channel are confirmed. Based on the results, the relation between inversion charge and WFV for different $V_{DS}$ is discussed.

II. DEVICE STRUCTURE

The structure of the MOSFET and TFET for WFV analysis is shown in Fig. 1(a). All of source, drain and channel materials consist of silicon. The body thickness ($T_{CH}$) of 10 nm, the channel length ($L_{GATE}$) of 50 nm, and the SiO2 gate oxide thickness ($T_{OX}$) of 1 nm are applied, respectively. P-type body doping ($N_{CH}$) of 1×1017 cm$^{-3}$ is set. Then, both silicon source and drain doping concentrations ($N_{S}$, $N_{D}$) are set as 1×1020 cm$^{-3}$ with same doping types arsenic in the MOSFET and opposite doping types boron/arsenic in the TFET. The gate area is split into 10 nm × 10 nm units considering the grain size of TiN and it is assumed to be an identical square shape [Fig. 1(b)]. In the real fabrication process, the sputtered TiN is mainly crystallized in <200> (60%) and in <111> (40%) which are corresponded to 4.6 eV and 4.4 eV WFs, respectively ^(25,26). All of specifications for device structure are summarized in Table 1.

Fig. 3. The ψMIN/ψMAX ratios in the MOSFET and TFET. The TFET shows high ψ variation compared with that of MOSFET. Especially, the ψ variation in the TFET shows larger $V_{DS}$ dependency.

Fig. 4. For different $V_{DS}$, electron densities in the channel surface for the (a) MOSFET, (b) TFET.

The electrical characteristics of the MOSFET and TFET are simulated by the Synopsys SentaurusTM. Shockley-Read-Hall (SRH) and dynamic nonlocal BTBT model are used for precise characteristics ^(27,28). The dynamic nonlocal BTBT model is essential to examine BTBT in the TFET, since it can dynamically determine and calculate all tunneling paths based on the energy band profile ^(29-32). In detail, the BTBT model is calibrated with experimental results ⁽³³⁾. The BTBT generation rate per unit volume (G) defined as in the uniform electric field limit where $F_{0}$ = 1 V/m and P = 2.5 for indirect tunneling ⁽³⁴⁾. The prefactor (A) and the exponential factor (B) are Kane parameters while the F is electric field ^(35,36). The extracted A and B parameters of the BTBT model are 4×10$^{14}$ cm$^{-3}$$s^{-1}$ and 9.9×106 V/cm, respectively, from the fabricated Si TFET. Also, modified local density approximation (MLDA) is used for including quantum phenomena. The applied models in the simulation are summarized in Table 2.

Fig. 5. $C_{GD}$ characteristics as a function of $V_{GS}$ with the various $V_{DS}$ in the (a) MOSFET, (b) TFET. In the TFET, as $V_{DS}$ increases, $C_{GD}$ is shifted to the positive direction due to intrinsic inversion characteristics.

Fig. 6. Illustrations of energy band diagram to explain channel inversion at high $V_{DS}$ for the (a) MOSFET, (b) TFET.

III. RESULTS AND DISCUSSION

Fig. 2(a) and (b) show the transfer characteristics of the MOSFET and TFET with various $V_{DS}$. For WFV evaluations, the 30 samples are simulated for each $V_{DS}$ with randomly generated TiN grains in the gate [Fig. 1(b)]. From the transfer characteristics, the drain current ($I_{D}$) variations are investigated for the maximum and minimum values of ID ($I_{MAX}$, $I_{MIN}$) according to the applied $V_{GS}$. Then, $I_{MIN}$/$I_{MAX}$ ratios are plotted as shown in Fig. 2(c) for the MOSFET and Fig. 2(d) for the TFET. If the $I_{MIN}$/$I_{MAX}$ ratio increases, it means that the ID variation decreases. For the MOSFET, the $I_{MIN}$/$I_{MAX}$ ratio depends on $V_{DS}$ values, when the gate voltage is applied less than $V_{GS}$ = 1.0 V. Over $V_{GS}$ = 1.0 V, the $I_{MIN}$/$I_{MAX}$ ratio gets closed to 1 regardless of $V_{DS}$ [Fig. 2(c)]. For the TFET, in contrast to the MOSFET, the $I_{MIN}$/$I_{MAX}$ ratio is not depending on $V_{DS}$ for under $V_{GS}$ = 1.0 V. Beyond $V_{GS}$ = 1.0 V, however, the higher the $V_{DS}$, the lower the $I_{MIN}$/$I_{MAX}$ ratio is confirmed. In summary, while MOSFET does not differ in ID variation according to $V_{DS}$ when $V_{GS}$ is highly applied, the TFET shows the association of ID variation according to $V_{DS}$ under the same conditions.

To analyze this phenomenon, the surface channel potentials (ψ) in the MOSFET and TFET are investigated. For 30 samples with WFV according to $V_{DS}$, the averaged ψ is extracted at 1 nm below the gate oxide. Then, after the maximum and minimum values of ψ (ψMAX, ψMIN) are evaluated from 30 samples, ψMIN/ψMAX ratio is calculated. Fig. 3 shows the values of ψMIN/ψMAX according to the $V_{DS}$ for the MOSFET and TFET. Over $V_{GS}$ = 1.0 V, it is found that the TFET has a larger ψ variation than that of the MOFSET. In other words, the ID variation depending on $V_{DS}$ in the TFET can be explained that the WFV affects the ψ variation in the channel area. Conversely, in case of the MOSFET, ID variation can be confirmed that the WFV has less impact on the ψ variation in the channel area.

In order to find out the cause of the channel potential variation depending on $V_{DS}$ in the TFET, rigorously, the densities of the electron charges (i.e., inversion charges) near gate oxide/channel interface are investigated [Fig. 4(a) and (b)]. The results show that the electrons over 1017 cm$^{-3}$ get piled near the channel beyond $V_{GS}$ = 1.0 V regardless of varied $V_{DS}$ in the MOSFET. However, in the TFET, the electron densities become reduced continuously near the channel while $V_{DS}$ goes up. Therefore, in the TFET, with decreasing $V_{DS}$, there are much more electrons in the channel, relatively. This can be understood that the channel potential modulation by WFV for lower $V_{DS}$ is pinned by many electrons supplied from drain. Then, to investigate the amount of inversion charges depending on the bias condition, $C_{GD}$ is evaluated for the MOSFET and TFET [Fig. 5(a) and (b)]. It is well corresponded to the results shown in Fig. 4(a) and (b) because $C_{GD}$ gets decreased while the $V_{DS}$ is increased. To compare both the MOSFET and TFET, it is checked that $C_{GD}$ dependency on $V_{DS}$ for the TFET shows larger than that of the MOSFET. In case of the MOSFET, the inversion charges in the channel is almost supplied by source for high $V_{DS}$ [Fig. 6(a)]. Therefore, there is less dependency on $V_{DS}$. Meanwhile, in the TFET, with low $V_{DS}$ or high $V_{GS}$, there is low band bending in the channel-to-drain junction, which implies a small energy barrier and high inversion charges in the channel [Fig. 6(b)]. Therefore, when low $V_{DS}$ is applied, the channel potential is rarely modulated by WFV and limits the ID variation from the source to the channel.

IV. CONCLUSIONS

This paper aim to study the WFV in TFET with various $V_{DS}$. As compared to the MOSFET, it has been revealed that inversion carriers of TFETs are provided from the drain. These inversion charges result in inhibiting channel band bending, which is variated by randomly distributed metal grains in the gate. Thus, the dominant dependency on $V_{DS}$ is found that the inversion charges from drain region pinned channel potential affected by the WFV.