Choi W. Y., Park B.-G., Lee J. D., Liu T.-J. K., Aug 2007, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Letters, doi: 10.1109/LED.2007.901273, Vol. 28, No. 8, pp. 743-745

Wang P.-Y., Tsui B.-Y., Jan 2016, Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure, IEEE Transactions on Nanotechnology, doi: 10.1109/TNANO.2015.2501829, Vol. 15, No. 1, pp. 74-79

Kim S. W., Choi W. Y., Kim H., Sun M. C., Kim H. W., Park B.-G., 2012, Investigation on hump effects of L-shaped tunneling filed-effect transistors, IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, 2012, doi: 10.1109/SNW.2012.6243306, pp. 1-2

Mishra A., Pattanaik M., Sharma V., 2013, Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits, Annual International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy, Kanjirapally, doi: 10.1109/AICERA- ICMiCR.2013.6575992, pp. 1-4

Knoch J., 2016, Chapter Eight - nanowire tunneling field-effect transistors, Semiconductors and Semimetals, http://dx.doi.org/10.1016/bs.semsem.2015.09.005, Vol. 94, pp. 273-295

Long P., Wilson E., Huang J. Z., Klimeck G., Rodwell M. J. W., Povolotskyi M., Jan 2016, Design and simulation of GaSb/InAs 2D transmission enhanced tunneling FETs, IEEE Electron Device Lett., doi: 10.1109/LED.2015.2497666, Vol. 37, No. 1, pp. 107-110

Dash S., Sahoo G. S., Mishra G. P., Mar 2016, Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate, Superlattices and Microstructures, https://doi.org/10.1016/j.spmi.2016.01.010, Vol. 91, pp. 105-111

Usha C., Vimala P., 2015, A tunneling FET exploiting in various structures and different models: A review, International Conference on Innova- tions in Information, Embedded and Communication Systems (ICIIECS), Coimbatore, doi: 10.1109/ICIIECS.2015.7192878, pp. 1-6

Dagtekin N., Mihai Ionescu A., May 2015, Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant CGD on Performance of TFET-Based Circuits, IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2014. 2377576, Vol. 3, No. 3, pp. 233-239

Zhong Y., Chen C., Huang Q., Wang Z., Ye L., Lou J., Huang R., 2018, Current Degradation and Delay Analysis of Series-Connected Circuits Based on Novel TFET Design, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, doi: 10.1109/ICSICT.2018.8565752, pp. 1-3

Sentaurus Device User Guide, ver. G-2012.06, Synopsys Inc.

Kane E. O., 1961, Theory of Tunneling, Applied physics lett., doi: 10.1063/1.1735965, Vol. 32, No. 1, pp. 83-91

Biswas A., Dan S. S., Royer C. L., Grabinski W., Ionescu A. M., 2012, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model, Microelectronic Engineering, doi: 10.1016/j.mee.2012.07.077, Vol. 98, pp. 334-337

Lee W., Choi W., Sept 2011, Influence of Inversion Layer on Tunneling Field-Effect Transistors, IEEE Electron Device Lett., doi: 10.1109/LED.2011.2159257, Vol. 32, No. 9, pp. 1191-1193

Safa S., Noor S. L., Khan M. Z. R., 2016, Simulation-based study on the effect of inversion charge layer on triple material double gate Tunnel FET, International Conference on Electrical and Computer Engineering (ICECE), Dhaka, doi: 10.1109/ICECE.2016.7853923, pp. 329-332

Vishnoi R., Kumar M. J., Feb 2015, An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion, IEEE Transactions on Electron Devices, doi: 10.1109/TED. 2014.2381560, Vol. 62, No. 2, pp. 478-484