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  1. (School of Electrical Engineering, Pukyong National University, 45 Yongso-ro, Nam-gu, Busan 48513, Korea)
  2. (Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea)

Tunnel field-effect transistor, TFET, nonlinear output characteristics, BTBT


Recently, tunnel field-effect transistor (TFET) has been researched widely due to their applicability for the low-power operations (1-4). In case of metal-oxide-semiconductor FET (MOSFET), which is conventionally utilized in the various circuits, there exists theoretical limit of 60 mV/dec subthreshold swing (SS) at the room temperature (RT) because its carrier injection is based on the thermionic emission (5,6). On the other hand, TFET is relatively independent to the Boltzmann distribution since the function tail is removed by forbidden gap. In addition, its dominant carrier injection mechanism is a band-to-band tunneling (BTBT) (7,8). Thus, the SS can be reduced to less than Boltzmann limit (i.e., 60 mV/dec at RT), which allows the supply voltage ($V_{DD}$) to be scaled down drastically maintaining high ON-state current ($I_{ON}$). However, TFET still has unsolved nonlinear current (NLC) problem in output characteristics especially at low drain bias ($V_{DS}$) (9,10). The NLC issue (i.e., small output conductance) significantly degrades the performance of TFET circuits such as rising and falling delay. However, the analysis of NLC have not been studied rigorously, yet.

This paper aims to study a fundamental origin of the NLC in output characteristics through technology computer-aided design (TCAD) simulations. Especially, the analysis of NLC is mainly performed to identify channel potential pinning in particular bias condition. The details about this study are as follow. After briefly explain the device process flow, BTBT model in the simulation tool is calibrated according to the parameters from the fabricated devices. Then, NLC phenomena in output characteristics are examined with the help of the energy band diagrams and channel potential. In addition, gate-to-drain capacitance ($C_{GD}$) and charge density in channel are also discussed.


First of all, before the TCAD simulations, a BTBT model calibration is performed based on experimental results. Fig. 1 shows the device structure of TFET. It is fabricated on a (100) $p$-type silicon-on-insulator (SOI) wafer. First, SOI thickness is thinned by using wet oxidation and wet etching processes. Active region is defined using photolithography and reactive ion etching (RIE) process. After that, gate oxide ($T_{OX}$ = 3 nm) is grown by dry oxidation. An n-type doped polycrystalline-Si gate is deposited by using low pressure chemical vapor deposition (LPCVD). After gate patterning, asymmetric source and drain (S/D) are formed through photolithography and ion implantation processes. In detail, BF$_{2}$ with 8×1014 cm$^{-2}$-dose, 7º tilt, and 10 keV-acceleration energy is used for source implantation while drain implantation is performed by As ions with the same condition. The dopant activation is implemented by rapid thermal process (RTP) with 900 ºC and 5 sec. Finally, as a back-end-of-line (BEOL) processes, a tetra-ethyl-ortho-silicate (TEOS) is deposited by plasma-enhanced CVD (PECVD) as an inter-layer dielectric (ILD) and metal layers (Ti/TiN/Al/TiN stacks) are deposited by physical vapor deposition (PVD) after contact hole formation. All the transfer characteristics are measured at $V_{DS}$ of 0.1 V and TCAD simulations are performed by using Synopsys SentaurusTM (11). A BTBT generation rate per unit volume ($G$) defined as

$$G=A\left(\frac{F}{F_{0}}\right)^{P} \exp \left(-\frac{B}{F}\right)$$

in the uniform electric field limit where $F_{0}$ = 1 V/m and $P$ = 2.5 for indirect tunneling (11). The prefactor ($A$) and the exponential factor ($B$) are Kane parameters while the F is electric field. The $A$ and $B$ values are chosen for the best fitting between the simulated and measured data (Fig. 1(b)) (12,13). From the results, it is found that both linear and log scales of the transfer characteristics are well matched. The extracted $A$ and $B$ parameters of the BTBT model in Si TFET are 4×10$^{14}$ cm$^{-1}$s$^{-1}$ and 9.9×10$^{6}$ V/cm, respectively.

Fig. 1. Cross-sectional views of TFET for BTBT calibration, (b) Calibrated transfer characteristics from simulation and measurement results for TFET.


Table 1. Simulation parameters





Body thickness

100 nm


Gate dielectric thickness

1 nm


Channel length

500 nm


Channel width

1 mm


Drain doping concentration

n-type 1020 cm-3


Body doping concentration

p-type 1015 cm-3


Source doping concentration

p-type 1020 cm-3

The simulated TFET for NLC analysis has same structure in Fig. 1(a) and it is designed to analyze output characteristics with the low $V_{DS}$, which is known as linear region. The simulated TFET features 100 nm-thick body thickness ($T_{Si}$), 1 nm-$T_{OX}$ and 500 nm channel length ($L$) to suppress short channel effects. In addition, an abrupt S/D doping profiles are assumed to minimize depletion region between S/D and channel. The specific information are summarized in Table 1. A dynamic nonlocal BTBT and a Shockley–Read–Hall generation-recombination models are used for the simulation (14).


The output characteristics of the TFET are studied by increasing gate voltage ($V_{GS}$) from 0.1 to 2.5 V with 0.4 V step (Fig. 2(a)). The output current can be classified into two characteristics. First, the drain current ($I_{D}$) cannot be increased regardless of $V_{GS}$ at a very low $V_{DS}$. In this operating condition, the $I_{D}$ is increased exponentially as a function of $V_{DS}$. Second, as the $V_{DS}$ increases, the increasing rate of $I_{D}$ gradually reduced and finally the $I_{D}$ is saturated. The NLC is confirmed at the first characteristic. The nonlinear characteristic severely degrades $I_{D}$ compared with linearly increasing case (e.g., MOSFET). The low current at low $V_{DS}$ is confirmed by transconductance curves in Fig. 2(b). Transconductance shows very small values near zero $V_{DS}$. The small transconductance significantly degrades the performance of TFET circuits such as propagation delay due to the low current drivability.

Fig. 2. (a) Output characteristics of TFET with various $V_{GS}$, (b) Transconductance as a function of $V_{DS}$ with the various $V_{GS}$.


Fig. 3. Extracted channel potential as a function of $V_{DS}$ with the various $V_{GS}$. The channel potential is extracted at 1 nm below the gate oxide according to the source-to-drain direction.


It is well known that the current in TFET is determined by the BTBT rate at source-to-channel junction. Therefore, in order to analyze NLC behavior, a channel potential is extracted as a function of $V_{DS}$ with 1.5 V and 2.5 V of $V_{GS}$ (Fig. 3). The results show that the channel potential can be classified into two regions. First, the $V_{DS}$ < $V_{GS}$ conditions are defined as non-saturation regions. Note that, the NLC is confirmed at this region. In this region, there is only 0.25 V-potential difference between two curves even though the increased amount of $V_{GS}$ is 1 V (i.e., from 1.5 V to 2.5 V). In other words, the channel potential is rarely modulated by the $V_{GS}$ and it is concluded that the $I_{D}$ is restricted by the pinned channel potential. Second, the $V_{DS}$ > $V_{GS}$ conditions are defined as saturation regions, in which the channel potential remains a constant although the $V_{DS}$ is increased. In addition, the saturation regions in terms of $V_{GS}$ could be also confirmed in Fig. 2(b), where the transconductance is zero. The difference of channel potential between two curves is about 1.0 V, corresponded to the $V_{GS}$ difference. It means that the channel potential is modulated proportionally to the applied $V_{GS}$ in this region.

Fig. 4. (a) Electron density distributions at the channel as the $V_{DS}$ increases. They are extracted along the depth direction as shown in the inset, (b) Extracted $C_{GD}$ as a function of $V_{DS}$ with the various $V_{GS}$. As the $V_{GS}$ increases, the $C_{GD}$ is shifted to the positive direction, (c) Illustration of energy band diagram with channel inversion.


In order to confirm the cause of the channel potential pinning in non-saturation region rigorously, the density of the electron charges (inversion charges) on channel is investigated (Fig. 4(a)). The results show that the electrons are piled on the channel at the 2.5 V of $V_{GS}$ and 0 V of $V_{DS}$. In addition, with increasing $V_{DS}$, the electrons in the channel are decreased. It means that the modulating channel potential is restricted by the inversion charges from drain. Then, to investigate the amount of inversion changes depending on the bias condition, the $C_{GD}$ is simulated with various $V_{GS}$ (Fig. 4(b)). It is well corresponded to the results shown in Fig. 4(a) that the $C_{GD}$ is decreased as the $V_{DS}$ is increased. In addition, when higher $V_{GS}$ is applied, $C_{GD}$ is decreased at more positive $V_{DS}$. The reason is that with low $V_{DS}$ or high $V_{GS}$, there is low band bending in the channel-to-drain junction, which implies a small energy barrier and high inversion charges in the channel (Fig. 4(c)) (14-16). Therefore, when a low $V_{DS}$ is applied, the channel potential is rarely modulated by $V_{GS}$ and limits the tunneling from the source to the channel, results in the NLC phenomenon.


This paper aim to study the NLC behavior in output characteristics which have been detected in TFET operation. When low $V_{DS}$ is applied in TFET, it has been revealed that inversion carriers of TFETs are provided from the drain. The inversion charges result in inhibiting channel band bending, which is modulated by $V_{GS}$. Thus, the dominant NLC mechanism is found that the inversion charges from drain region confined the channel modulation.


This research was supported in part by the Brain Korea 21 Plus Project, in part by the MOTIE/KSRC under Grant 10080575 (Future Semiconductor Device Technology Development Program), and in part by the NRF of Korea funded by the MSIT under Grant NRF-2019M3F3 A1A03079739 and NRF-2019M3F3A1A02072091 (Intelligent Semiconductor Technology Development Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.


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Jang Hyun Kim

was born in Seoul, South Korea, in 1985. He received BS. Degrees from Korea Advanced Institute of Science (KAIST), Daejeon, South Korea, in 2009, and M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, in 2011 and 2016, respectively.

From 2016 to 2020, he joined SK Hynix inc. He is currently an Assistant Professor with the School of Electrical Engineering, Pukyong National University.

Sangwan Kim

was born in Daegu, South Korea, in 1983. He received the B.S., M.S., and the Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, South Korea, in 2006, 2008, and 2014, respectively.

He had been a post-doctoral scholar at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA, from 2014 to 2017.

Since 2017, he has been a Faculty Member with Ajou University, Suwon, South Korea, where he is currently an Associate Professor with the Department of Electrical and Computer Engineering.