Mobile QR Code QR CODE

REFERENCES

1 
Park S. K., Jul. 2015, Technology scaling challenge and future prospects of DRAM and NAND flash memory, Proc. International Memory Workshop (IMW), pp. 1-4DOI
2 
Park J. M., Hwang Y. S., Kim S. W., Han S. Y., Park J. S., Kim J., Seo J. W., Kim B. S., Shin S. H., Cho C. H., Nam S. W., Hong H. S., Lee K. P., Jin G. Y., Jung E. S., Dec. 2015, 20nm DRAM: a new beginning of another revolution, Proc. International Electron Devices Meeting (IEDM), pp. 676-679DOI
3 
Kim S. K., Lee S. W., Han J. H., Lee B., Han S., Hwang C. S., Aug. 2010, Capacitors with an equivalent oxide thickness of < 0.5 nm for nanoscale electronic semiconductor memory, Advanced Functional Materials, Vol. 20, No. 18, pp. 2989-3003DOI
4 
Kwon H. M., Kwon S. K., Jeong K. S., Oh S. K., Oh S. H., Choi W. I., Kim T. W., Kim D. H., Kang C. Y., Lee B. H., Kirsch P., Lee H. D., Aug. 2014, A correlation between oxygen vacancies and reliability characteristics in a single zirconium oxide metal-insulator-metal capacitor, IEEE Transactions on Electron Devices, Vol. 61, No. 8, pp. 2619-2627DOI
5 
Kim K., Dec. 2005, Technology for sub-50nm DRAM and NAND flash manufacturing, Proc. International Electron Devices Meeting (IEDM), pp. 323-326DOI
6 
Kim K., Chung U. I., Park Y., Lee J., Yeo J., Kim D., Mar. 2012, Extending the DRAM and FLASH memory technologies to 10nm and beyond, Optical Microlithography XXV, International Society for Optics and Photonics, Vol. 8326, pp. 832605DOI
7 
Kim B. Y., Lee K. J., Ji Y. H., Lee S. M., Koo J. H., Do K. W., Park K. W., Ahn J. H., Park W. Y., Feb. 2015, Method for fabricating capacitor with high aspect ratio, U.S. Patent, No. 8,962,437Google Search
8 
Jegert G., Kersch A., Weinreich W., Lugli P., Feb. 2011, Monte Carlo Simulation of Leakage Currents in TiN/ZrO2/TiN Capacitors, IEEE Transactions on Electron Devices, Vol. 58, No. 2, pp. 327-334DOI
9 
Jegert G., Popescu D., Lugli P., Häufel M. J., Weinreich W., Kersch A., Jan. 2012, Role of defect relaxation for trap-assisted tunneling in high-κ thin films: A first-principles kinetic Monte Carlo study, Physical Review B, Vol. 85, No. 4, pp. 045303DOI
10 
Pešić M., Knebel S., Cho K., Jung C., Chang J., Lim H., Kolomiiets N., Afanas’ev V. V., Mikolajick T., Schroeder U., Jan. 2016, Conduction barrier offset engineering for DRAM capacitor scaling, Solid-State Electronics, Vol. 115, pp. 133-139DOI
11 
2017, Sentaurus Device SimulatorGoogle Search
12 
Cho H. J., Kim Y. D., Park D. S., Lee E., Park C. H., Jang J. S., Lee K. B., Kim H. W., Ki Y. J., Han I. K., Song Y. W., Nov.-Dec. 2007, New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs, Solid-State Electronics, Vol. 51, No. 11-12, pp. 1529-1533DOI
13 
Bhattacharya K., Feb. 2016, On the dependence of charge density on surface curvature of an isolated conductor, Physica Scripta, Vol. 91, No. 3, pp. 035501DOI