I. INTRODUCTION

Increasing the storage capacitance ($C_{s}$) is one of the most important research topics of downscaling dynamic random access memory (DRAM) cells. However, unfortunately, as DRAM technology node decreases down to 1x nm, it becomes more challenging to maintain $C_{s}$ around 25 fF/cell^[1]. Conventionally, two ways of improving $C_{s}$ have been generally utilized: introducing novel high-$k$ materials to storage capacitors and modifying storage capacitor structures. The former boosts $C_{s}$ per effective surface area ($A_{eff}$) of a storage capacitor while the latter increases $A_{eff}$ itself^[2].

State-of-the-art DRAM cells use high-aspect-ratio (HAR) cylindrical storage capacitor structures filled with high-$k$ materials, which is problematic in the following two aspects^[3]. First, storage capacitors using high-$k$ materials suffer from high leakage current ($I_{leak}$) due to high trap density ($N_{T}$)^[4]. It is a serious problem considering that the retention time of a DRAM chip is heavily dependent on the $I_{leak}$ of several leaky cells^[5]. Second, HAR cylindrical structures need cutting-edge etching technologies to obtain vertical etch profiles. However, as the aspect ratio of DRAM storage capacitors increases, their etch profiles become more analogous to the bowed ones^[6,7]. Thus, HAR storage capacitors tend to have the top critical dimension ($CD_{TOP}$) different than the bottom one ($CD_{BOT}$) as shown in Fig. 1(a) unlike the ideal case where $CD_{TOP}$ is equal to $CD_{BOT}$ to obtain the largest $A_{eff}$ as shown in Fig. 1(b). The key process steps of Fig. 1(a) and Fig. 1(b) are shown in Fig. 2(a) and Fig. 2(b), respectively. A mold layer is dry-etched and then filled with a bottom electrode layer. Subsequently, the removal of the mold layer is followed by the deposition of high-$k$ material and top electrode layers. The etched profiles of the mold layer determine the value of $CD_{BOT}$ / $CD_{TOP}$, whose ideal value is 1. Thus, it is meaningful to investigate the influence of etch profiles on both $C_{s}$ and $I_{leak}$ of 3-D DRAM storage capacitors. However, most of previous studies have focused on either of them assuming 1-D or 2-D structures^[8-10]. In this manuscript, based on technology computer-aided design (TCAD) simulation, the effects of etch profiles of 3-D DRAM HAR cylindrical storage capacitors will be investigated in terms of both $C_{s}$ and $I_{leak}$^[11].

Fig. 1. Bird’s eye and cross-sectional views of (a) a 3-D HAR cylindrical storage capacitor whose $CD_{BOT}$ / $CD_{TOP}$ < 1, (b) a 3-D HAR cylindrical storage capacitor whose $CD_{BOT}$ / $CD_{TOP}$ = 1, (c) a planar storage capacitor.

Fig. 2. Key process steps of a storage capacitor in (a) the ideal, (b) real case.

II. SIMULATION METHODOLOGY

Fig. 1 summarizes the storage capacitor structures simulated in this manuscript. Metal-insulator-metal (MIM) capacitors where a ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film sandwiched between TiN electrodes have been used for sub-60-nm technology nodes^[12]. Simulation parameters have been carefully calibrated by experimental data^[9]. For calibration, planar storage capacitors are simulated as shown in Fig. 1(c). Table 1 summarizes calibrated simulation parameters.

Dominant $I_{leak}$ mechanisms of TiN/ZAZ/TiN (TZAZT) capacitors are Poole-Frenkel emission (PFE) and trap-assisted tunneling (TAT)^[8-10]. Fig. 3 shows the conduction band edge ($E_{c}$) profile of a TZAZT capacitor including charge transport mechanisms. $I_{leak}$ flows across the capacitor in the following two steps. First, conduction electrons tunnel from an electrode into the traps in the ZAZ layer through TAT. The trap level energy ($E_{VO}$) depending on oxygen vacancies determines $I_{leak}$. Second, trapped electrons are detrapped and then injected into the opposite electrode through either PFE or TAT depending on the applied electric field intensity. Under weak electric field, TAT is dominant while PFE is dominant under strong electric field. Those processes are successfully implemented in our TCAD simulation by using local PFE and nonlocal inelastic/elastic TAT models. Fig. 4 shows that our simulation results match well with experimental data under various temperature conditions^[9]. It is noteworthy that the experimental data measured at low electric field is ignored in our steady-state TCAD simulation because it is transient relaxation current depending on deep traps^[9].

Fig. 3. $E_{c}$ profile of a TZAZT capacitor including charge transport mechanisms. CBO corresponds to conduction band offset between TiN and ZAZ layers. The dashed line and circle mean $E_{VO}$ and a trapped electron, respectively. $q$ and $V$ are elementary charge and applied voltage, respectively.

Fig. 4. Calibrated simulation data compared with experimental data^[9]. Even if simulation parameters are calibrated at room temperature, simulation data match well with experimental data over wide temperature range. It is noteworthy that leakage current at low electric field is ignored during our steady-state simulation parameter calibration because it is originated from transient relaxation current^[9].

The calibrated 2-D simulation results have been extended into 3-D simulation. The storage cap structures in Fig. 1(a) and Fig. 1(a) are simulated and their dimensions are summarized in Table 2.

III. SIMULATION RESULTS AND DISCUSSION

Fig. 5 shows the $I_{leak}$ and $C_{s}$ with various $CD_{BOT}$ / $CD_{TOP}$’s normalized by $I_{leak}$ ($I_{0}$) and $C_{s}$ ($C_{0}$) with $CD_{BOT}$ / $CD_{TOP}$ = 1, respectively. $I_{leak}$ is measured when top electrode voltage ($V_{TOP}$) is 2.0 V. It is observed that $C_{s}$ / $C_{0}$ decreases linearly while $I_{leak}$ / $I_{0}$ increases nonlinearly as $CD_{BOT}$ / $CD_{TOP}$ decreases. For the analysis of this phenomenon, Fig. 6 shows the electric field ($E$) profiles of the storage capacitors in the ideal and real cases when $V_{TOP}$ is fixed at 2.0 V. The maximum $E$ is found at the corner edges corresponding the dominant $I_{leak}$ paths. Also, it is clearly observed that the maximum E increases as $CD_{BOT}$ / $CD_{TOP}$ decreases. It makes the upper electrode sharper, which increases maximum $E$ ^[13]. Thus, as $CD_{BOT}$ / $CD_{TOP}$ decreases, the surface charge density increases at the sharpened region of the top electrode, and E increases accordingly.

Fig. 5. $I_{leak}$ (measured at $V_{TOP}$ = 2.0 V) and $C_{s}$ normalized by $I_{0}$ and $C_{0}$.

Fig. 6. $E$ contours of storage capacitors whose (a) $CD_{BOT}$ / $CD_{TOP}$ = 1, (b) $CD_{BOT}$ / $CD_{TOP}$ = 0.625, following the A-A’ cross-sections in Figs. 1a and 1b, respectively. Enlarged views of (c) Fig. 6(a) and (d) 6(b). The arrows mean the vector representation of $E$. $V_{TOP}$ is fixed at 2 V.

Finally, we extracted the average and maximum $E$ with the variation of $CD_{BOT}$ / $CD_{TOP}$ and calculated $A_{eff}$ as the interface surface area of the bottom electrode and the dielectric layer which represents a smaller area than the top electrode side as shown in Fig. 7. The average $E$ is calculated as the average of the electric field for all points in the dielectric layer to compare the effect with the local maximum $E$. $E_{0}$ means the $E$ extracted at $V_{TOP}$ = 2.0 V when $CD_{BOT}$ / $CD_{TOP}$ is 1. $A_{0}$ means the $A_{eff}$ when $CD_{BOT}$ / $CD_{TOP}$ is 1. As expected, the $I_{leak}$ shown in Fig. 5 does not correspond to the average $E$ but match well with the maximum $E$. Following the charge transport models used in this simulation such as PFE and TAT, $I_{leak}$ is exponentially proportional to $E$, which means that $I_{leak}$ is determined mainly by maximum $E$ rather than average $E$.^[8-10]. On the other hand, the dependence of $C_{s}$ on $CD_{BOT}$ / $CD_{TOP}$ is explained by the $A_{eff}$ which is linearly proportional to $C_{s}$.

Fig. 7. $E$ and $A_{eff}$ normalized by $E_{0}$ and $A_{0}$, respectively. $V_{TOP}$ is fixed at 2.0 V.

IV. CONCLUSIONS

The influence of the etch profiles of a 3-D DRAM storage capacitor on $I_{leak}$ and $C_{s}$ has been investigated by using full 3-D TCAD simulation. As $CD_{BOT}$ / $CD_{TOP}$ decreases, $I_{leak}$ increases exponentially while $C_{s}$ decreases linearly. Thus, the etch profiles of a storage capacitor should be made as steep as possible for the optimization of state-of-art HAR storage capacitor in terms of both $I_{leak}$ and $C_{s}$.