I. INTRODUCTION

With ongoing scientific and technological advancements, the demand for analog integrated circuits (ICs) is rising rapidly in emerging fields such as 5G communication, the Internet of Things (IoT), and smart wearable devices. To meet the increasing requirements of circuit design, continuous improvements in Electronic Design Automation (EDA) technology are essential. While digital ICs have seen the development of highly automated EDA software, the automation level in EDA tools for analog ICs remains relatively low ^[1]. Within this context, automated layout generation technology for analog ICs, a critical aspect of analog EDA efforts, has become a key focus of current research.

Significant progress has been made in automated layout generation techniques. BAG ^[2] draws inspiration from the digital integrated circuit design flow, devising a set of templates for transistor layout and wiring. Using parameterized code design and synthesis, it generates actual layouts. MAGICAL ^[3], leveraging artificial intelligence, pioneers a fully automated analog IC layout system. Starting from unannotated netlists, it performs automated layout constraint extraction and device generation, followed by layout and placement optimization, culminating in wiring to produce the final GDSII layout. ALIGN ^[4] emulates the hierarchical recognition and processing performed by humans for transistors, basic units (e.g., differential pairs, current mirrors), modules (e.g., operational transconductance amplifiers), and systems (e.g., RF transceivers). In layout, ALIGN ^[4] integrates algorithmic design, template design, and machine learning (ML) design approaches, enabling the creation of layouts with a complexity level comparable to that of expert designers.

However, for transistors requiring high matching accuracy, generic layout techniques may not be suitable. Transistor matching ensures that multiple transistors operating under similar conditions exhibit nearly identical electrical characteristics, such as threshold voltage (Vt), transconductance (gm), and drain current (Id). Any mismatch among transistors can lead to performance degradation, increased power consumption, or even circuit failure. In advanced technology nodes, layout-dependent effects (LDEs) are among the factors causing variations in transistor performance ^[5,6,7]. Among these, the well proximity effect (WPE) ^[7] can be observed in nanometer-scale CMOS nodes. By either shifting the well edge away from the device or maintaining equal well-to-well spacings between matched devices, the mismatch caused by WPE can be minimized. Length of diffusion (LOD) ^[8] results in stress variations on transistors due to changes in the length of the diffusion region. Oxide definition (OD) spacing and width ^[9] alter the stress in a transistor due to variations in spacing between the OD regions (active areas). Utilizing identical unit cells for matched devices can help disregard all LDEs except LOD and WPE ^[10]. Therefore, the study focus lies in optimizing LOD and WPE mismatch through placement techniques.

To mitigate mismatches, specialized layout placement algorithms for matched devices must be designed to enhance overall circuit performance. In the layout placement of matched devices, previous works serve as important references. The work of ^[11] proposed a universal algorithm for fitting arbitrary capacitance ratios in Common-Centroid (CC) unit capacitor arrays. This algorithm effectively addresses non-integer and identical ratios to minimize mismatches. The work of ^[12] introduced a general algorithm for automated CC placement of IC component arrays. Initially, it constructs an algorithm to obtain placement schemes close to optimal solutions, followed by an iterative algorithm to search for even better placement schemes. The work of ^[13] represents nodes as vertices and source-drain connections between transistor fingers as edges, establishing a ``half diffusion graph'' to maximize diffusion sharing while generating the optimal two-dimensional CC layout. The work of ^[14] incorporates considerations for thermal effects, minimizing device mismatches induced by thermal gradients while satisfying symmetry and CC constraints. The work of ^[15] proposed a constructive, performance-aware CC layout and routing algorithm for transistor arrays. Their method specifically considers performance variations induced by stress based on Length of Diffusion (LOD), maximizes diffusion sharing, and mitigates the impacts of parasitic resistance and electromigration (EM). The work of ^[16] reviewed numerous previous works on CC layout and examined scenarios where non-CC layouts might be more suitable than CC layouts.

Our contributions can be summarized as follows:

1. We have designed a comprehensive algorithmic system that spans from netlist and initial placement to final placement. This system achieves efficient layout design while also ensuring compatibility with other algorithms and scalability.

2. The designed algorithm is utilized to transform transistors under Common-Centroid (CC) layout and to determine the merging situation of adjacent transistors to minimize the layout area by using the PyCell API, which can adapt to different technology nodes.

3. Through experimentation, it has been empirically demonstrated that our system and algorithms, compared to existing methods, can optimize transistor layout area while ensuring device matching and reduce parasitic effects.

In the next section, we will provide an overview of the system for automated matching placement generation throughout the entire process. Section III outlines the improvements made in our work regarding matched device placement algorithms. Section IV discusses the experimental results. We conclude in Section V with a summary and future development.

II. OVERVIEW OF THE AUTOMATED MATCHING PLACEMENT GENERATION

The proposed automated placement generation for matching devices consists of five functional modules: the reading module, the identification module, the measurement module, the placement module, and the compression module. The input to the system includes the netlist file of the circuit and the GDSII file of the circuit layout, and the output is the GDSII file after layout compression. The entire system flowchart is shown in Fig. 1.

Fig. 1. System flowchart of the proposed automated placement generation for matching devices.

The primary function of the reading module is to parse the netlist and GDSII files, establishing a correspondence between the devices of netlist and the devices of layout. The devices used here are pcells. To ensure the proper functioning of the algorithm, the device must have at least M1 contacts on both the source (S) and drain (D) terminals. Besides, other pcell settings may affect the final performance of the algorithm. For instance, if post-layout routing is considered, the poly switch of the device's gate (G) should be turned on, and corresponding M1 contacts should be added, leading to an increase in the final inter-row spacing. Specifically, dummy devices also need to be included in the netlist. They are characterized by connections between the source and drain or between the source and gate. Identifying these characteristics allows for distinguishing dummy devices from other devices. The netlist file contains information such as device names, network connections to device ports, device types, and sizes, whereas the GDSII file encompasses process layers, geometric data, and hierarchical structures. By processing these files, the reading module gathers information on each device in both the netlist and layout, subsequently linking them together. During this process, automatically annotated layout devices are used to match the devices in the netlist. The device information (including both netlist and layout device information) that matches successfully will be used later in the PyCell API.

The primary function of the identification module is to determine the matching relationships between devices. This module inputs the circuit netlist and identifies matching relationships among devices, such as differential pairs and current mirrors. The identification method employed is based on the graph traversal technique ^[4], which establishes and explores the topological relationships between devices. Through this process, the module locates related devices and further identifies whether these devices exhibit matching relationships.

The primary function of the measurement module is to measure various geometric dimensions within the GDSII file. For individual devices, the measurement module can assess overall dimensions, the dimensions of each process layer, the center point position, and the port positions of the device. For each group of matching devices, it can measure the dimensions, centroids, and areas of the matching device group. Regarding the entire layout, the measurement module can determine the dimensions and area of the overall layout.

The main function of the placement module is to perform CC placement of devices based on identified matching relationships and measured data. In the field of CC layout, relevant work includes but is not limited to ^{[12,13,14,15,16]}. We have designed a simple and efficient algorithm according to the mindset of layout engineers. For the matching relationship of current mirrors, based on the CC placement principle, priority is given to placing the master device in the middle and the slave devices on both sides. For the matching relationship of differential pairs, the devices to be matched are first arranged in one to two rows, and then arranged in an ``ABBA'' pattern and follow the CC placement principle.

The primary function of the compression module is to further compress the layout of devices, reducing the area occupied by the matching device layout while ensuring matchability. The implementation of this module will be detailed in the next section.

The proposed system accomplishes the entire process from netlist and layout input to final layout output, resulting in a compact placement. Additionally, the system exhibits high compatibility, allowing the algorithms in the identification and placement modules to be easily replaced with those used in other works.

III. DEVICE MATCHING AND COMPRESSION TECHNIQUES IN AUTOMATED PLACEMENT GENERATION

After performing common-centroid placement of the devices, a significant gap often remains between them, specifically in the form of inter-row (Y Space) and inter-column (X Space) spacing. By reducing these spacings, the devices can be further compressed while maintaining their matching, resulting in a more compact placement. The compression process is illustrated in Fig. 2.

Fig. 2. Diagram of compression by reducing the inter-row spacing (Y Space) and inter-column spacing (X Space) of transistors.

Inter-column spacing can be compressed for adjacent transistors using port merging or well merging technology. Well merging technology supports the merging of four types of regions: N-well, P-well, N+ region, and P+ region. In contrast, port merging technology not only includes well merging but also supports the merging of active regions and metal regions. The performance of these two techniques is demonstrated in Fig. 3. However, unlike inter-column spacing, inter-row spacing can only be compressed by merging the wells.

In port merging technology, adjacent devices share the same port, requiring identical port nets, thus avoiding triggering Layout versus Schematic (LVS) errors. In well merging technology, adjacent devices share the same well, and the spacing between them is minimized without triggering Design Rule Checking (DRC) errors. On the Python platform, Synopsys's PyCell framework provides a freely accessible API for creating layouts without DRC errors. During design, PyCell API functions can succinctly express the relative positions of geometric objects, read design rules from technology files as constraint functions, and use them during layout and routing processes. To elaborate, during the design process, the PyCell API can read design rules from the technology file and incorporate them into constraint functions, which are then invoked during layout and routing. If there is no corresponding technology file for the process, the technology file must be manually created. For instance, designers can specify placing two devices as close as possible, and the PyCell API will automatically adjust the distance between the two devices while satisfying DRC rules for all layers in both devices. In well merging technology, the spacing between adjacent devices is computed by the PyCell API.

To ensure the matching of devices and prepare for subsequent port merging, the swap operation between the source port and the drain port of the MOS transistor is necessary. Fig. 4 shows the source-drain port swap operation of the MOS transistor under different finger conditions. By swapping ports, the port nets at the boundaries can be altered, enabling common-centroid (CC) placement of ports or ensuring identical neighboring port nets of adjacent transistors.

Before compression, it is necessary to transform all devices by rotating, mirroring, and swapping source and drain ports to ensure the consistency of device orientations and that ports of different nets share the same centroid. The premise of port merging is that the two ports share the same net. However, sometimes the matching placement of transistors cannot guarantee that the nets of each pair of adjacent ports are identical. To ensure matching, only one of the two techniques---well merging or port merging---can be used during the compression process. Therefore, it is necessary to determine whether it is reasonable to use the port merging technique, which may be better than the other technology. We propose a generalized algorithm to address this issue, and the algorithm flow is shown in Fig. 5. The relevant variable descriptions are presented in Table 1.

Fig. 5. Flow diagram of the proposed algorithm for determining the transistor merging strategy.

Firstly, we need to obtain the number of rows and columns of the transistor array and store their values in variables ${m\_end}$ and ${n\_end}$, respectively. The algorithm iterates starting from the bottom-left transistor to the top-right transistor, sequentially iterating through all transistors within each row, and then moving to the next row after completing iteration within a row. During each iteration, the row and column indices of the currently iterated transistor are stored in variables ${m}$ and ${n}$, respectively. At the beginning of the iteration, the bottom-left transistor is considered the first row and first column transistor, and the values of variables ${m}$ and $n$ are initialized to 1. The variable count tracks the number of iterations executed and is initialized to 0.

During each iteration, the placement of transistors in the first column of each row is determined based on the value of the count variable. Subsequently, the placement of transistors in the remaining columns is sequentially determined according to the port merging technique and the swapping operations of drain and source ports. If no valid transistor placement satisfies the port merging condition during the iteration, the process is terminated prematurely, and a new iteration is initiated with the count variable incremented by one. If the iteration process completes successfully and the count value is less than 2, it indicates that the port merging technique can be applied to compress the inter-column spacing of the transistor array, and the algorithm terminates. Conversely, if the count value is greater than or equal to 2, it signifies that the well merging technique can be applied to compress the inter-column spacing of the transistor array, and the algorithm terminates.

After the judgment step, the devices have not only achieved common-centroid (CC) placement of their centroids, but also CC placement of their ports. Furthermore, if the judgment result permits the use of the port merging technique, adjacent ports of devices in each row will share the same net. This configuration necessitates only minimal device movements for subsequent compression, thereby obviating the need for additional steps.

Following the outlined procedure, the appropriate compression technique is determined, and the devices are primed for compression. The centroid position of the device group prior to compression is retained as the new centroid position post-compression. Transistors closest to the centroid position are prioritized for merging to minimize inter-column and inter-row spacings, progressively extending to all transistors, with the movement pattern illustrated in Fig. 2. The movement distance for device compression is dictated by data from the system's measurement module and the specified spacing between designated layers as required by the compression module. For instance, the distance necessary for trench merging is calculated using PyCell, while port merging necessitates a complete overlap of two ports with a port centroid distance of zero. During the compression process, the total movement distance of symmetric devices with respect to the centroid on the x-axis or y-axis remains equal. Post-compression, the placement of transistors becomes notably compact, as will be clearly demonstrated in the experimental results discussed in the subsequent section.

IV. EXPERIMENTAL VALIDATION OF COMPRESSION PERFORMANCE

To validate the performance of our system and algorithm, we selected the complete differential operational amplifier circuit structure, as illustrated in Fig. 6. This circuit encompasses an n-type current mirror, two identically sized p-type current mirrors, and a matched structure of the differential pair.

Fig. 6. Schematic of a differential operational amplifier.

We constructed the circuit using the TSMC 65nm process and exported the netlist and layout of the circuit as input data for our system, as shown in Fig. 7. The netlist contains at least four components: device names, device types, nets connected to the devices, and device parameters. The layout corresponds to the netlist, including these four components. In this sample, we set the channel length and the single finger channel width of each MOSFET to 400 nm and 500 nm, respectively.

To evaluate the compression performance of our system, we compared the layout of each matched circuit structure before and after compression. The layout comparison of the differential pair structure is illustrated in Fig. 8, where each device has a finger count of 4, and inter-column spacing is compressed using the port merging technique. The layout comparison of the p-type current mirror is shown in Fig. 9, with each device having a single finger, and inter-column spacing is compressed using the port merging technique. Finally, the layout comparison of the n-type current mirror is displayed in Fig. 10, where each device has a single finger, and inter-column spacing is compressed using the well merging technique.

Table 2 presents a comparison of the layout size and area before and after compression for each experimental case. It is evident that the layout of each matched circuit structure has been significantly reduced in both size and area. The area reduction after compression, compared to before compression, is 54.10% for the differential pair matching structure, 52.51% for the N-type current mirror matching structure, and 77.86% for the P-type current mirror matching structure. Across these three experimental cases, the average area reduction exceeds 50%.

The placement of the circuit before and after compression is shown in Fig. 11. Before compression, the circuit layout size was $22.94 \times 14.35$ $\mu$m, with an area of 329.19 $\mu$m$^2$. After compression, the circuit layout size reduced to $14.99 \times 11.26$ $\mu$m, with an area of 168.79 $\mu$m$^2$. Compared to the uncompressed version, the compressed layout area decreased by 48.73%, indicating a significant compression effect.

We conducted a comparative analysis of our approach against Align ^[4], focusing on the performance of devices under different compact layouts. The routing between device ports was manually performed using the same wire width for all connections. Fig. 12 illustrates the resulting layouts generated by both methods, while Table 3 provides a detailed comparison of their post-layout performance metrics. Our approach achieved a 23% reduction in layout area, with a final area of 192.586 $\mu$m$^2$ compared to 250.306 $\mu$m$^2$ for the Align method. Additionally, our layout demonstrated a slight improvement in gain, increasing to 32.959 dB, along with an enhanced unity gain frequency (UGF) of 427.757 MHz. The total parasitic capacitance was also reduced by approximately 20%, underscoring the effectiveness of our method in optimizing both space and performance.

V. CONCLUSIONS

This paper presents an intelligent system for the automated placement generation of matching structures, such as current mirrors and differential pairs, with a focus on enhancing layout efficiency and compactness. The proposed system integrates several functional modules, including reading, identification, measurement, placement, and compression, to achieve a fully automated placement process from the initial netlist to the final design.Experimental validation was conducted using a fully differential operational amplifier designed with the TSMC 65nm process. Comparative analysis of device layouts before and after the application of the compression module demonstrated significant improvements in placement compactness. The layout area of the differential pair, n-type current mirror, and p-type current mirror structures was reduced by 54.10%, 52.51%, and 77.86%, respectively, achieving an average area reduction exceeding 50%. The results indicate that our system effectively addresses the challenges of common-centroid layout for matching devices, ensuring high matching accuracy while not only minimizing layout area but also reducing parasitic effects. Furthermore, compared to the Align ^[4] method, our approach demonstrates improved performance, offering enhancements in gain, unity-gain frequency, and overall layout efficiency. The results indicate that our system effectively addresses the challenges of common-centroid layout for matching devices, ensuring high matching accuracy and minimizing layout area. Future work will focus on extending the compression capabilities of the system to other matching devices, such as capacitors and resistors, and expanding support to include FinFET structures. This advancement will further enhance the applicability and versatility of the system in modern analog IC design.