I. Introduction

Low-dropout voltage regulators (LDOs) have found widespread application in system-on-a-chip (SoC) design because they provide minimal voltage ripple, fast transient response, compact area requirements, and cost-effectiveness. As the industry trend shifts the development of digital circuits operating at near-threshold supply voltages to mitigate power consumption. So, traditional analog LDOs (ALDOs), composed of analog amplifiers, encounter design challenges. In contrast, digital LDOs (DLDOs) can operate at lower supply voltages, consuming less energy, facilitating seamless integration, and optimizing SoC performance.

The DLDO typically operates at two distinct frequencies: the fast-sampling frequency and the slow-sampling frequency. Initially, the fast-sampling frequency rapidly stabilizes over or under-shooting states. When the feedback voltage deviates significantly from the target voltage, coarse pass gates are controlled to create large current steps. Hence, the coarse state demands brief operation at a high frequency to ensure low power consumption. Conversely, the slow-sampling frequency controls the operation of fine pass gates, which implement small current adjustments suited for handling subtle changes characteristic of steady states. So, employing a single type of sampling frequency can lead to suboptimal power efficiency. In the ^[1,2], DLDOs operate using an external clock signal. Consequently, DLDOs can remove the need for clock-generating blocks but require additional clock pins. Other architectures ^[3-5] use voltage-controlled oscillators (VCOs) as the clock generation block.

The proposed design employs a single VCO utilizing an automatically varying control voltage block. As a result, this approach eliminates the need for additional control voltage or external clock pins.

II. Architecture

An overall block diagram of the proposed DLDO is illustrated in Fig. 1. The DLDO comprises three comparators. The first comparator detects the difference feedback output voltage (FB_OUT) with the medium reference voltage (REF_M) and then, generates the VCO gain controller’s "SEL" signal. The second and third comparators are utilized to identify over-shooting or under-shooting states. During over-shooting or under-shooting events, the coarse pass gates adjust the voltage with wide steps to approach the target voltage. And the fine pass gates precisely adjust to become the target voltage.

The digital controller section operates based on the outputs of comparators and the VCO, controlling both coarse and fine pass gates.

The VCO is configured with the negative gain operation, as depicted by the positive voltage output (OUTP) signal in Fig. 2. As the control voltage decreases, the frequency increases.

A single-to-differential amplifier and a multiplexer are utilized to establish bidirectional K$_{\mathrm{VCO}}$ behavior, allowing automatic adjustment of the VCO's input control voltage based on the difference between reference and feedback voltages.

Lastly, resistors are utilized to generate the DLDO's feedback voltage, with resistor values determined by the quiescent current. Quiescent current serves as a critical figure of merit (FOM) measurement, whereas lower quiescent current yields a smaller FOM. The C$_{\mathrm{load}}$(load capacitor) is set at 2 pF.

Fig. 1. Block diagram of proposed DLDO with a VCO.

Fig. 2. Relationship between the FB_OUT and VCO output frequency in proposed DLDO.

III. Circuit Description

The digital controller consists of coarse and fine control sections, each incorporating a binary to thermal-weighted code converter. The converter increments one bit per clock cycle based on a counter, while a thermal-weighted 256-bit signal controls each pass gate, implemented through 256 transistors. Thermal-weighted code lends itself well to parallel processing. Given the independence of each bit, parallel operations become feasible, proving advantageous in swift computations.

The VCO gain controller manages the value of the control voltage. The first comparator’s input voltages are FB_OUT and REF_M. When FB_OUT falls below (rises above) REF_M, the ``SEL'' signal switches to ‘1’ (‘0’), and the output of the single-to-differential amplifier becomes OUTP (OUTN). Illustrated in Fig. 3 is the relationship between the clock frequency and FB_OUT response. As the gap between FB_OUT and REF_M values widens, the control voltage decreases, leading to a gradual increase in the VCO's output frequency. This adaptive operation optimizes power consumption by dynamically adjusting the operating frequency, eliminating the need for external control voltage pins. The single-to-differential amplifier consists of two operational transconductance amplifiers (OTAs) and resistors. The single-to-differential amplifier is designed for linear operation within the VCO's operating ranges, enabling the VCO gain controller to maintain linearity. The total power consumption of the VCO gain controller is 104 ${\mu}$W, whereas that of a single VCO’s power is 267.3 ${\mu}$W at 403 MHz. The VCO generates frequencies 238 MHz to 484 MHz, and power consumption varies from 160.7 ${\mu}$W to 267.3 ${\mu}$W. Thus, the proposed design offers a 163.3~${\mu}$W advantage over conventional approaches.

The second and third comparators share a common input, which is FB_OUT, while high reference voltage (REF_H) and low reference voltage (REF_L) are fed into each of their inputs. The FB_OUT over the REF_H or under the REF_L, then the digital controller operating the coarse pass gates. Then when the FB_OUT is in between REF_H and REF_L, the digital controller operates the fine pass gates.

Fig. 3. Concept of the relationship between the clock frequency and FB_OUT response.

VI. Simulation Result

The 65 nm CMOS process was used to implement the proposed DLDO that controls the output to 1 V from 1.2~V supply. Fig. 4 shows the layout of the proposed DLDO. Upon stabilization of LDO_OUT, the frequency proportionally decreases are shown in Fig. 5. Additionally, in Fig. 5(a) the voltage oscillations are due to the digital controller adjusting the code, which sequentially turns the pass gates on and off. As indicated in the graph, the peak-to-peak ripple voltage (${\Delta}$V$_{\mathrm{ripple}}$) is 598 ${\mu}$V. Table 1 summarizes the simulated performance metrics. Different from conventional design, this work used a single VCO. The quiescent current is 11.3 ${\mu}$A. So, a peak current efficiency at 20 mA is 99.93%. When the I$_{\mathrm{LOAD}}$ is from 10 mA to 20 mA, LDO_OUT reaches a steady state and the frequency settles at 782 ns. On the other hand, from 20 mA to 10 mA, the transient time is 430 ns. The proposed DLDO shows the lowest 15 fs of FOM and gets the largest peak current efficiency.

Fig. 4. Layout of proposed DLDO.

Fig. 5. Simulation results of (a) LDO_OUT; (b) frequency; (c) CLK signal.

Table 1. Performance comparison

V. Conclusions

This work introduces a DLDO structure designed to adaptive manage circuit frequency utilizing a single VCO. Through the combination of a single-to-differential amplifier and a multiplexer, the VCO gain controller selects one of the bidirectional K$_{\mathrm{VCO}}$ properties. Adaptive regulation of the control voltage enables fast transition times during under or over-damped states. Simulated results show a peak current efficiency of 99.93%, a quiescent current of 11.3 ${\mu}$A, a chip area of 0.099 mm$^{2}$, a FOM is 15 fs, and a transition response of 782 ns.