I. Introduction

For many decades, there has been a continuous effort to enhance the electrical performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) in low-power applications, primarily through the adoption of FinFET or gate-all-around (GAA) structures ^[1-5]. However, these structures do not enable steep switching in transfer curves due to a theoretical limit of 60 mV/decade subthreshold swing (SS) caused by the Boltzmann tail in the source region. To address this challenge, tunnel field-effect transistors (TFETs) have been investigated to eliminate the Boltzmann tail and achieve SS values below 60 mV/decade ^[6-19]. This extremely low SS indicates very low static power consumption, which can lead to significant performance improvements in low-speed applications. For example, MAC (Multiply-Accumulate) units require high computational throughput with low power consumption, making this device suitable for such applications ^[20].

Furthermore, as MOSFETs have scaled down to the nanoscale, the doping concentration in the MOSFET channel has increased to enhance the gate's control over the channel. However, this increase in doping concentration has introduced issues such as poly/metal-grain granularity (MGG). These variations make it challenging to produce integrated circuit chips with a high yield during the manufacturing process ^[16-19].

To address these challenges, doping-less TFETs that operate by forming an energy band using the charge trap within the gate insulator has been studied. The gate insulator of the proposed device consists of a triple dielectric stack (ONO: SiO$_{2}$-Si$_{3}$N$_{4}$-SiO$_{2}$). Electrons trapped in the nitride layer of the ONO dielectric form an energy band between the source and the channel. When considering work function variation (WFV) related to metal grain, it is expected that there is no immunity against current variations compared to junctions formed by doping. However, this immunity is not confirmed and needs rigorous validation ^[17-19].

In this paper, we investigate the electrical characteristics of WFV in a dopingless TFETs with an ONO stack. When employing the ONO structure and ONO programming, it is anticipated that the impact on the channel will be reduced, even in the presence of WFV.

II. Device Simulation

The device configuration of the charge trap TFETs employed in this simulation is illustrated in Fig. 1. The ONO dielectric layers are comprised of SiO$_{2}$, Si$_{3}$N$_{4}$, and SiO$_{2}$. The thickness of the bottom oxide layer (T$_{\mathrm{OXB}}$) is 1~nm, the top oxide layer (T$_{\mathrm{OXT}}$) measures 6 nm, and the nitride layer (T$_{\mathrm{N}}$) is 2 nm thick. All source, drain, and channel materials are made of silicon (Si). To mitigate the impact of the short channel effect (SCE), the channel length (L$_{\mathrm{Channel}}$) is set at 60 nm. There is no doping in the tunnel barrier that carries the current. However, doping has been introduced in the source region to reduce contact resistance. The body contact doping (N$_{\mathrm{S}}$) is 5${\times}$10$^{18}$ cm$^{-3}$ (p-type), drain doping (N$_{\mathrm{D}}$) is 5${\times}$10$^{18}$ cm$^{-3}$ (n-type), and body doping (N$_{\mathrm{sub}}$) is 1${\times}$10$^{15}$ cm$^{-3}$ (p-type). We have placed a p+ region behind the source area to facilitate the smooth charge/discharge of holes. This p+ region does not need to be added to each device individually; it can be shared among multiple devices.

The material employed in the WFV model was TiN, with WFV values of 4.4 eV and 4.6 eV, each representing 40 % and 60 % probabilities, randomly distributed on the gate. A total of 50 samples were produced for each simulation run and subsequently assessed. The characteristics of the doping-less TFET with charge trap were simulated using Synopsys Sentaurus$^{\mathrm{TM}}$. The Shockley-Read-Hall (SRH) and dynamic nonlocal BTBT model were used for accurate characterization. The dynamic nonlocal BTBT model is essential, as it can dynamically determine and calculate all tunneling paths based on the energy band profile. In detail, the BTBT model was calibrated with experimental results, as shown in Fig. 2(a). To calculate the BTBT generation rate (G) per unit volume at the uniform electric field limit, Kane’s model was used [Eq. (1)] ^[28].

The prefactor (A) and the exponential factor (B) are Kane parameters, while F represents the electric field. For accurate simulation, we calibrated the model parameters by extracting current from the fabricated planar TFET. The calibrated parameters are as follows: F$_{0}$ = 1 V/m, P = 2.5 for an indirect BTBT, A$_{\mathrm{Si}}$ = 4.0 ${\times}$ 10$^{14}$ cm$^{-3}$·s$^{-1}$, and B$_{\mathrm{Si}}$ = 9.9 ${\times}$ 10$^{6}$ V/cm are the Kane parameters of Si, and F denotes the electric field. The program rate in the ONO dielectric was also calibrated based on a fabricated Metal-SiO$_{2}$-Si$_{3}$N$_{4}$-SiO$_{2}$ capacitor. In the inset of Fig. 2(b), the simple fabrication processes are shown. Each thickness of the dielectric is the same as in the proposed device. The flat band shifts (${\Delta}$V$_{\mathrm{FB}}$) were extracted with various program times. The electron tunnel mass was calibrated with the ONO capacitors' electron trapping rate, as shown in Fig. 2(b). To calibrate the electron trapping rate, the electron tunnel mass was fitted with ${\Delta}$V$_{\mathrm{FB}}$.

Fig. 1. Structure of the doping-less tunnel field-effect transistor (TFET) with charge trap layer.

Fig. 2. Structure of the doping-less tunnel field-effect transistor (TFET) with charge trap layer.

III. Simulation Results

Fig. 2(c) represents the energy band at 0.5 V of drain voltage (V$_{\mathrm{DS}}$) when cut into the ONO line. When program bias is applied in gate, the electrons on drain are moved to the channel and when gate voltage is applied, the electrons are trapped to the nitride region. When programmed, it is found that the energy band in the nitride region has risen by about 4 eV from initial state. And the energy band in the programmed nitride region raises the energy band of the source. Fig. 2(d) shows the transfer characteristics of the charge trap TFET with various V$_{\mathrm{DS}}$. There is no drain induced current enhancement. depending on the V$_{\mathrm{DS}}$, so the short channel effect (SHE) can be excluded. And the minimum SS is 28.59 mV/dec of V$_{\mathrm{DS}}$ = 0.1 V, 29.01 mV/dec of V$_{\mathrm{DS}}$ = 0.5~V and 34.62 mV/dec of V$_{\mathrm{DS}}$ = 1.0 V. Thus, we found that the SS values for V$_{\mathrm{DS}}$ changes are below 60 mV/dec. The proposed device is a low power device that can operate at a low gate bias. We confirmed the BTBT generation of the device. Since the proposed device is made of dopingless, as seen in inset of Fig. 2(d), the BTBT region is formed at edge of gate region. Fig. 3(a) shows a BTBT rate of the charge trap TFET from 2 nm to 15 nm of substrate thickness (T$_{\mathrm{sub}}$). The proposed device does not form a tunnel barrier through doping, but rather the tunnel barrier region changes with voltage [Fig. 3(b) and (c)]. In other words, electrons are programmed into the charge trap region to form a tunnel barrier, but the depletion region near the Si channel changes due to the operating voltage, causing variations in BTBT occurrence rates. Due to these characteristics, the downside is that high current is not exhibited. However, even if the substrate thickness varies with the process, the current characteristics are determined by voltage, resulting in minimal current variation. Consequently, it has the advantage of high reliability and can be used to create devices that are insensitive to PVT variations.

In Fig. 4(a), a sequential hole program is executed by applying a pulse with a gate voltage of -8 V. After performing a 1-step program, the current is examined at V$_{\mathrm{GS}}$ = 0.5 V. If the current value is lower than the target threshold voltage (V$_{\mathrm{t}}$, @ 10$^{-12}$A/\foreignlanguage{greek}{${\mu}$}m) additional programming is carried out [Fig. 4(b)]. The configuration of the mixed-signal circuit is depicted in Fig. 4(c). For the NOR/NAND pass gate section, the circuit is constructed using high-performance MOSFETs with good I$_{\mathrm{ON}}$ characteristics, while the stack section is implemented with the proposed TFETs. The reason for evaluating a mix of MOSFETs and TFETs in Fig. 4(c) is that using two-stage TFETs would result in excessive degradation due to low current drive and WFV. If the entire circuit were constructed using TFETs, the reduced current drivability of TFETs would result in higher resistance, leading to a decrease in the output voltage margin. However, since the TFET's characteristic changes due to WFV were fully reflected, as shown in the simulation, a precise evaluation was conducted. Thus, the effect of reducing variation with the proposed device's program has been thoroughly demonstrated. In the NOR/NAND section, out of the two devices connected in series, one is constructed using TFETs. This configuration, due to the low I$_{\mathrm{OFF}}$ characteristics of TFETs, results in a truth table based on input, as shown in Fig. 4(d). The output values are inverted based on each input, and the corresponding improvement in voltage variation is measured.

In Fig. 5, the n-type and p-type characteristics of the proposed device are illustrated. For cases Fig. 5(a) and (c), the program time and voltage were fixed at 8 V and 0.01 sec, respectively, to depict the scatter of the transfer curve concerning WFV. In cases Fig. 5(b) and (d), results are shown where the program pulse was adjusted using the bias scheme from Fig. 4(a) to reduce the V$_{\mathrm{t}}$ variation. In the case of n-type, it exhibited a 0.1 V decrease in V$_{\mathrm{t}}$ variation, while for p-type, there was a 0.04 V reduction in variation.

In Fig. 6, the operation of the proposed device's NAND gate is depicted based on the presence or absence of programming. The bottom-most device was constructed using MOSFETs to reduce resistance, while the rest of the devices were formed using the proposed TFETs. The variation in transition time due to V$_{\mathrm{t}}$ differences was observed. Specifically, it can be observed that before programming, ${\Delta}$t (time variation) reduced from 10.7 ${\mu}$s to 6.3 ${\mu}$s [Fig. 6(a) and (b)]. A similar reduction was also observed in NOR, decreasing from 11.1 ${\mu}$s to 6.2 ${\mu}$s [Fig. 6(c) and (d)]. This ultimately translates to a minimum 41 % improvement in the operating frequency margin.

Fig. 3. (a) Transfer curves of proposed TFET. BTBT generation rate on the source region; (b) 10 nm; (c) 5 nm of substrate thickness.

Fig. 4. (a) Program sequence for achieving the target V_t; (b) Program hole density based on the gate pulse; (c) NOR and NAND gates with mixed usage of MOSFETs for reduced resistance circuits; (d) Truth table of logic gate.

Fig. 5. n-type: (a) initial; (b) programmed, p-type; (c) initial; (d) programmed TFET.

Fig. 6. NAND/NOR gate transient simulation: (a) conventional NAND; (b) proposed NAND; (c) conventional NOR; (d) proposed NOR.

Table 1. Parameters of TCAD simulation

IV. Conclusion

In conclusion, this study has provided valuable insights into the electrical characteristics of dopingless TFETs featuring ONO gate insulator stacks. The research has demonstrated the potential benefits of employing ONO structures to reduce the impact of WFV on the channel, paving the way for more reliable TFET-based devices. The study's exploration of TFETs' immunity to WFV and current variations compared to doping-based junctions has important implications for future device design and optimization. These findings have the potential to enhance the performance and reliability of TFETs in various applications, particularly in low-power applications. In other words, the proposed device's current can be precisely tuned, allowing for consistent current output despite changes in process, voltage, and temperature. This characteristic makes it highly applicable in logic circuits that require stable characteristics, such as bandgap generators and temperature sensors ^[29-31]. Overall, the findings of this study hold promise for the development of more robust and efficient TFET-based devices, and the insights gained may lead to advancements in semiconductor technology, ultimately benefiting a wide range of industries and applications.