I. Introduction

Research on ultrawideband (UWB) technology commenced in 2002, coinciding with the authorization of the U.S. Federal Communications Commission (FCC) to allocate the microwave frequency range from 3.1 GHz to 10.6 GHz for civilian applications ^[1]. UWB technology has been used in several applications because of its ability to communicate between wireless devices in proximity, as well as to measure the distance between them. In particular, the advantages of high resolution, high penetration, and low power consumption of UWB radar have led to the development of numerous applications, such as security sensors, wall penetration detection, surveillance, and human motion detection, including rear occupant alert (ROA) sensors ^[2-7]. The front end of a UWB radar receiver must operate with a robust performance, including low power consumption, low noise performance, and high gain, over a wide range of frequencies. In addition, the signal strength varies with the distance from the detection object, necessitating a large dynamic range (DR). Therefore, a circuit that can control amplification gain based on detection distance is essential ^[8].

The low-noise amplifier (LNA), serving as the active balun stage, must exhibit a high gain and a low noise figure (NF) across a broad frequency spectrum. The design process requires careful consideration of the tradeoffs among input matching, NF, gain, bandwidth, and linearity. A balanced architecture is favored over an unbalanced architecture because of its enhanced robustness against common-mode noise, including disturbances from the power supply and substrate noise provided by differential signaling ^[9]. Consequently, a balun is required to convert a single-ended RF signal into a differential signal. A well-known topology for a broadband active balun uses a common gate (CG)-common source (CS) pair as the active balun ^[9-15]. The CG-CS active balun LNA allows for an efficient interface with the antenna, minimizes the chip area, achieves high gain for better system-wide noise performance, and minimizes NF.

However, previous studies ^[11,12] have suffered from asymmetry owing to the natural imbalance of the CG and CS stages. Kim ^[9] proposed the addition of gate resistance at the cascode transistor of the CS stage to counter-offset the differential gain and phase imbalance, but suffered from an additional noise source (resistor) and limited compensation frequency range. The work in ^[13] utilized a current bleeding technique to obtain equal currents in CG and CS load resistors; thus, a balanced load and differential output can be obtained. However, it is limited by the large power consumption of the CS transistor by the current-bleeding circuit. In addition, they require a high supply voltage to ensure sufficient headroom for all the devices, making them unsuitable for low-power applications.

RFVGA is also critical for the noise and sensitivity of the receiver front-end performance, because it provides limited gain ^[9-15]. Furthermore, because the received signal strength can vary significantly owing to the varying distance between the radar and the object, the system response must provide fine gain variations while maintaining a wide bandwidth to maximize the dynamic range of the receiver ^[16]. A previous study ^[17] utilized a linearized mutual conductance block with a four-transistor transconductance cell to achieve a high gain and a wide range of variable gains at a lower supply. However, the linear gain control range and accuracy are limited by this approximation formula. In ^[18], a closed-loop structure was used to achieve a wide linear gain-control range and high linearity. However, the limited bandwidth of this structure renders it unsuitable for UWB systems. The RFVGA proposed in ^[19] implements a fully differential topology with shunt peaking and feedback to remove common-mode noise and even-order signals, improve the input secondary intercept point (IIP2) characteristics and achieve a wide bandwidth. However, the feedback controlling the loop gain of the circuit must consider the effect of the input resistance on the signal in a cascaded system.

In this study, we propose a broadband UWB radar receiver consisting of an LNA and a two-stage RFVGA. The LNA employs an active balun structure that reuses the intrinsic gain of the CS stage to increase the transconductance of the CG stage to achieve low noise and high gain without sacrificing the noise and power efficiency. The 2-stage RFVGA includes a variable gain function to obtain additional gain based on the differential signal from the LNA, while simultaneously ensuring signal quality according to the radar detection distance. A back-to-back inverter is proposed as the regeneration amplifier to further enhance the signal strength in addition to the intrinsic gain ($g_{m}r_{o}$ per stage, ^[20]) of the two-stage cascaded common-source amplifiers (RFVGA). The same regeneration scheme also effectively compensated for the differential (gain and phase) imbalance of the active balun-LNA. The frequency response of the entire front end is staggered with the low-pass response of the LNA, quasi-high-pass response of the RFVGA 1st-stage, and band-pass response of the RFVGA 2nd-stage. This staggering provides the wide bandwidth and large gain in a power efficient manner when implemented with the low-cost 0.13 ${\mu}$m CMOS technology. With the aforementioned techniques, the designed UWB receiver front-end provides 13-26 dB gain ranges over a wide bandwidth of 6-9 GHz while ensuring a gain and phase imbalance of less than 1 dB and 4$^{\circ}$, respectively.

This paper is structured as follows: Section II elucidates the composition and attributes of the LNA integral components of the UWB receiver front end. In Section III, we examine the variable gain control, gain, and bandwidth enhancement of the proposed RFVGA, which features a back-to-back inverter regenerative positive feedback structure and a PMOS-based switch. Section IV presents the simulation results of the proposed UWB receiver front end with a detailed discussion, and Section V provides concluding remarks.

II. Front-end of UWB Reiver and CG-CS Active Balun LNA

Fig. 1 shows the proposed receiver front-end system as part of a sampling-based impulse radio UWB radar receiver ^[7,15,16]. The front-end offers a wideband, large gain, low differential phase and gain imbalance, and variable gain performance; thus, it is suitable for UWB radar transceiver chips operating in the 6-9 GHz band. The LNA is based on the conventional CG-CS active balun LNA ^[15] but improves the current (power) efficiency by utilizing the gain of the CS stage as the transconductance boosting factor of the CG stage. The first stage is a CG-CS active balun LNA, which achieves low noise and performs a balun (single-to-differential) function for an efficient interface with single-ended antennas. Compared with transformer-based baluns ^[21,22], the proposed LNA minimizes the use of the chip area along with a high gain (>10 dB) for improved system-level noise performance. The RFVGA, as the second and third stages of the front end, includes a variable gain function to obtain additional gain based on the differential signal at the front end, while simultaneously ensuring signal quality as a function of radar detection distance.

Fig. 1. Block diagram of the proposed UWB radar receiver front-end.

Fig. 2 shows a schematic of the proposed LNA. The CG stage provides an input match and a noninverting signal at the CG output, whereas the signal phase is inverted by 180$^{\circ}$ in the CS stage. The output of the CS stage is fed back to the CG stage and the effective transconductance ($g_{m,CG}$) by the gain of the CS stage. Thus, the negative feedback connection relaxed the input-matching condition without increasing the current of the CG stage or the transistor size.

Fig. 2. CG-CS active balun-LNA.

Previous studies ^[11,12,15] unanimously utilized the scaling up of the CS transconductance to minimize the noise contribution from the CS transistor, while cancelling the noise of the CG transistor. For the case shown in Fig. 2, the following equation is ensured to maintain an equal DC gain for the non-inverting and inverting outputs.

However, unequal transistor sizing and subsequent asymmetries in design parameters, such as parasitic capacitance and output impedance, result in significant imbalances at high frequencies, especially around the cut-off frequency range. While neglecting the poles at the drain node $\left(v_{b}\right)$ of the CS transistor located at relatively higher frequencies than the non-inverting and inverting outputs (differential outputs), the transfer function from node $v_{x}$to both outputs can be derived as ^[11]

We can define the imbalances in gain and phase in terms of the design parameters as follows:

Fig. 3 shows the gain and phase imbalance of the active Balun-LNA topology (Fig. 2). The simulation results were based on reasonable design parameters satisfying the equal DC gain condition in (1), as aforementioned. As shown in Fig. 3, the gain imbalance reaches 1.42 dB and the phase imbalance reaches 10$^{\circ}$ at the end of the 3-dB cutoff frequency, which requires further corrections at the later stages.

Fig. 3. Gain and phase imbalance of the active Balun-LNA.

III. Proposed RFVGA

Fig. 4 and 5 show schematics of the 1st- and 2nd-stage RFVGA, respectively. A two-stage RFVGA is necessary to minimize the noise contributions from the subsequent track and hold (T/H) circuit for equivalent time sampling ^[7]. The CS amplifier with a cascode transistor is at the core of the RFVGA, as shown in Fig. 4 and 5. Assuming that the cascode stage perfectly transfers the current from the CS transistor to the output, the low-frequency gain of the single-stage CS amplifier can be obtained by multiplying the transconductance by the output resistance. To accommodate the UWB spectrum bands up to 10 GHz, the amplifier should be power-hungry with low output resistance and large transconductance.

Fig. 4. Proposed 1st-stage RFVGA structure.

Fig. 5. Proposed 2nd-stage RFVGA structure.

Fig. 6. Current-efficiency $g_{m}/I_{D}$ and unity-gain frequency $g_{m}/C_{GS}$ ratio of the NMOS device with 16 μm/0.13 μm (W/L)0.13 μm.

Fig. 6 shows the $g_{m}/I_{D}$(current-efficiency) and $g_{m}/C_{GS}$ (unity-gain frequency) of the NMOS device with 16 ${\mu}$m/0.13 ${\mu}$m (W/L). The plot shows that the speed of the transistor is proportional to overdrive voltage $\left(V_{ov}=V_{GS}-V_{TH}\right)$, and the current-efficiency is inversely proportional to $V_{ov},$ reaching 26 at $V_{ov}=-300mV.$ However, the stringent requirement of the amplifier bandwidth (>10 GHz for each stage) dictates that we must bias the transistor during strong inversion. With a large $g_{m}/I_{D}$ratio, the required power consumption is prohibitively high.

The two-stage RFVGA in our proposed work is a cascoded CS topology, which provides a high-pass (1st-stage), and band-pass (2nd-stage) frequency response along with a variable gain and regeneration circuit to enhance the gain with limited $g_{m}/I_{D}$. As a regeneration gain stage, the back-to-back inverter was employed at the cascode and output nodes of each RFVGA stage. The proposed circuit further improves the gain through limited positive feedback and successively corrects the gain and phase imbalances. Because the regeneration inverter may cause unwanted oscillations, the inverter is sufficiently small such that its loop gain is significantly smaller than the unity gain.

The output stage includes a variable gain. The PMOS transistors for the variable gain are absent in the output stage but found in a node separated from the output stage by two series-connected resistors. This prevents the output stage from including the input parasitic component of the next stage and from further dropping the pole position of that node using the transistor for variable gain. The output stage has a low-pass response owing to the resistors and parasitic capacitance of the resistors and transistors. An inductor at the output stage was adopted to boost the load impedance, which widened the bandwidth. An output impedance structure consisting of $R_{L1},$ $R_{L2},$ and $L_{1}$ was chosen for the broadband behavior. The $R_{L1}$ resistor provides a constant load regardless of the change in frequency, and the provided load had a low value, allowing the design to have a sufficiently small RC time constant at the output stage. The output impedance, consisting of $R_{L2}$ and $L_{1},$ has a low quality-factor (Q), which ensures a wide bandwidth. To ensure variable gain, the PMOS transistor reduces the magnitude of the output impedance consisting of $R_{L1}$ and $L_{1}$according to the desired variable gain setting.

The gains of the 1st-stage and 2nd-stage of RFVGA, ignoring inverter regeneration, are expressed by (5) and (6), respectively.

where $R_{P}$ is the effective resistance of the PMOS transistor and $C_{L}$ in (5) is the parasitic capacitance present at the output stage. $R_{P}$ is high when the PMOS transistor is off. Each RFVGA stage provides 2-bit controlled PMOS transistors; thus, it can provide a total of 16 steps in gain.

The 1st and 2nd-stages of the RFVGA were designed with the same structure; however, the second stage was changed to the bandpass response of the LC resonator structure by adding a capacitor at the output stage. The designed device sizes of the balun LNA and RFVGA are summarized in Table 1.

Table 1. Device dimension

IV. Simulation Results

The front-end of the UWB receiver is designed in TSMC 0.13 ${\mu}$m CMOS technology. Fig. 8 shows the layout of the front end with buffers to interface with the off-chip ports. The UWB receiver front-end chip has an area of 905 ${\times}$ 740 ${\mu}$m, with an active area of 680 ${\times}$ 520~${\mu}$m. The buffer was designed as a pseudo-differential source follower and was used to drive the load. Fig. 7(a) shows the simulated input and output impedance-matching performance of the front end with buffers. The simulated $S_{11}$ and $S_{22}$ are lower than -10 dB over the frequency range of 6 to 10 GHz and buffer with an output impedance of $1/g_{m,buffer}=50\Omega$ Fig. 7(b) shows the simulated voltage gain. The maximum and minimum voltage gains of the proposed front-end were 26 and 13 dB, respectively. The variation in the voltage gain with the sensing distance was controlled in 16 steps, as explained previously.

Fig. 7(c) shows the simulated NF of the proposed front end and buffer. Within the 3 dB bandwidth of the system, the measured minimum NF is 8.72 dB at the 8 GHz frequency, whereas the simulated minimum NF at the setting with the minimum voltage gain increases to 10.5 dB at the same frequency. This is because of the thermal noise introduced by the resistance present in the PMOS at the output end of the RFVGA to achieve variable gain.

Fig. 7(d) shows the linearity performance of the proposed circuit with two tones injected at 6 GHz and 6.2 GHz. The 3rd order intercept point (IIP₃) of the front-end is -8.4 dBm.

Fig. 7(e) and (f) show the gain and phase errors between the inverting and non-inverting outputs, respectively. Gain and phase errors are less than ${\pm}$1 dB and 4 deg, respectively, in maximum gain mode and operating frequency (6 to 9 GHz). The simulated performance of the proposed receiver front end for the UWB radar is summarized in Table 2.

Fig. 7. Performance of the UWB receiver front-end: (a) input matching ($S_{11}$) and output matching ($S_{12}$) ; (b) voltage-gain; (c) noise figure (NF); (d) third-order intercept point (IIP₃) at maximum gain setting; (e) gain imbalance; (f) phase imbalance.

Fig. 8. Layout of proposed UWB receiver front-end.

Fig. 9. UWB receiver front-end performance with PVT variation: (a) input matching ($S_{11}$) and output matching ($S_{22}$) by process variation; (b) voltage-gain by process variation; (c) noise figure (NF) by process variation; (d) third-order intercept point (IIP₃) at maximum gain setting by temperature variation; (e) voltage gain by temperature variation; (f) NF by temperature variation.

The UWB receiver front-end must provide robust performance against process, voltage, and temperature (PVT) variations. Fig. 9 shows the simulated results at room temperature (27$^{\circ}$) and at different temperatures of -30$^{\circ}$C and 90$^{\circ}$C for typical-typical (TT), slow-slow (SS), and fast-fast (FF) process corners to ensure the robustness of the circuit. The input and output matching (Fig. 9(a)and (d) ) demonstrates the robustness against PVT variations. $S_{22}$does not change at TT, SS, and FF corners, and is sufficiently smaller than -10 dB without frequency change even when the temperature changes. The power gain (Fig. 9(b)and (e)) is simulated to be 30.18 dB, 26 dB, and 20.61 dB at -30$^{\circ}$, 27$^{\circ}$, and 90$^{\circ}$, respectively. The SS corner provides the maximum power gain of 24.13 dB, while the FF corner provides 25.69 dB. Fig. 9(c)and (f) shows the NF temperature dependence and corner simulation results. The minimum NF at -30$^{\circ}$, 27$^{\circ}$, and 90$^{\circ}$ are 8.27 dB, 8.72 dB, and 10.24 dB, respectively. The NF variation at the SS and FF corners is due to the gain variation. All the performances show small variations in the corner and temperature simulation results, which shows that they are robust to PVT variation.

Table 3 presents the simulated performance of the proposed UWB receiver front-end, highlighting its advantages in comparison to recently reported designs. The proposed circuit demonstrates the highest gain while maintaining low power consumption. Additionally, it offers the flexibility to adjust the gain based on the detection range requirements.

V. Conclusions

In this study, we present the front-end architecture of a UWB radar receiver. A CG-CS active balun LNA was employed to reduce the power consumption and provide better input matching by negative feedback of the gain of the CS stage to the input of the CG stage. The proposed two-stage RFVGA cascaded to an LNA is a fully differential CS amplifier with additional gain amplification and error correction performed using back-to-back inverter regeneration techniques at the cascode and output stages. By switching on/off the PMOS transistors present at the output stage of the RFVGA, the gain can be adjusted according to the radar reception sensitivity.

The front-end of the proposed UWB radar receiver was implemented in a 0.13 ${\mu}$m CMOS, and simulation results showed a maximum power gain of 26 dB, variable gain of 13 to 26 dB, minimum NF of 8.72 dB, and an IIP3 above -8.4 dBm while consuming 12 mW of power from a 1.2 V supply. Comparing the measurement results with recently published balun-LNAs, the proposed balun-LNA without an on-chip inductor showed a competitive performance with the lowest power consumption.