I. Introduction

Biopotential signals recorded from neural interface systems are widely used to understand, diagnose, and treat neurological disorders such as epilepsy or Parkinson's disease, and related research is actively in progress ^[1-8]. In these neural interfaces, there are important considerations during the design process. First, low power consumption is required in the multi-channel interface circuit to limit the excessive heating of surrounding tissue and to lessen the burden on the wireless power delivery circuits. Considering several tens to hundreds of channels to interface with the microelectrode array, only a few microamperes of current can be allocated to the individual front-end circuits. Second, sufficient amount of amplification gain as well as low noise performance is required in the recording circuits to resolve and process weak desired neural signals with sufficient quality. These signals which can be categorized as local field potentials (LFP) and action potentials (AP) have various bandwidths between sub-Hz to a few kHz with amplitudes from several ${\mathrm{\mu}}$V to a few mV, so it is important that the desired signal can be recorded with programmable gain and bandwidth. Typically, an integrated input referred noise (IRN) of around 5 to 10 ${\mathrm{\mu}}$Vrms is required for frequencies of 1 Hz - 10 kHz ^[2,3]. Another consideration in the design is that recent neural interfaces are designed with bidirectional signal conditioning capability which consist of a stimulation unit ^[4] operating at high voltage to stimulate the target area with a precise controlled current and a recording unit that monitors and records signals to interpret the changes and patterns in the resulting neural activity. However, in an operation scenario where both the stimulation and recording units operate concurrently, a large common-mode (CM) artifact signal may affect the recording unit due to a direct conduction path from the stimulation unit through the cerebrospinal fluid (CSF) ^[5-8]. The CM signal that affects the recording section can be tens to hundreds of times larger than the desired recorded signal, and can range from hundreds of mV to several V ^[6,7]. Therefore, as this voltage is large enough to saturate the recorder, a method to resolve this issue is needed. While several analog domain approaches have previously been reported, one of the solutions is to simply block and disable the recording unit when the stimulation unit operates ^[9]. However, this option has the disadvantage that recording is interrupted for some duration and important signal information may be lost. Another method is to use feed-forward based CM cancellation ^[6,7]. In this case, signal removal is possible only in a limited range, and there is a disadvantage where significant degradation occurs in the noise performance due to the cancellation circuitry ^[8].

In this work, a low-power, low-noise neural recording analog front-end (AFE) with a feedback-based common-mode cancellation loop (CMCL) ^[10] is proposed with notable modification. The AFE features programmable gain and bandwidth to support both LFP and AP signals through a highly reconfigurable architecture. The paper is organized as follows. Section Ⅱ explains the AFE architecture and the design of key circuits. Section Ⅲ shows the measurement results of the implemented IC and compares with previous similar works while Section IV concludes the paper.

II. Circuit Design

Fig. 1 shows the overall structure of the proposed AFE circuit. The first stage (G$_{\mathrm{M1}}$) of the low-noise amplifier (LNA), which has the greatest impact on the total noise of the AFE, is designed as an inverter-based operational transconductance amplifier (OTA) using a current reuse technique ^[2]. The second stage (G$_{\mathrm{M2}}$) employs a 5-transistor fully-differential OTA structure to secure the output range. In addition, the LNA is allocated 80% of the total power consumption of the AFE to achieve low noise performance. The feedback-based CMCL using a current mirror structure A$_{\mathrm{CM}}$ with rail-to-rail output to tolerate large artifacts produced by the stimulator is designed to reject signals of the same magnitude as the supply voltage.

For the control of the high-pass bandwidth of the overall AFE frequency response, narrow-band buffers (NBB) ^[11] are placed in the feedback loops of the LNA and the programmable gain amplifier (PGA). Another NBB is placed in between the LNA and the PGA for the low-pass bandwidth control. Thus, the AFE can process both LFP and AP signals or separately handle them. After the low-pass NBB, the gain can be adjusted using the PGA. Adjusting the input capacitor has a significant effect on the overall noise performance, and adjusting the feedback capacitor with a switch has the disadvantage of changing the bandwidth differently than intended for each gain setting. Therefore, the proposed PGA is designed to keep the bandwidth constant by changing the feedback capacitor and using the adaptive Miller compensation technique ^[12]. Since the bandwidth does not change due to the change in the gain of the PGA, the overall bandwidth of the AFE is determined solely by the NBB blocks.

Fig. 1. Overall simplified structure of the proposed AFE (the actual signal paths are differential).

1. Common-mode Cancellation Loop (CMCL)

The proposed CMCL used to cancel large CM artifacts at the input is shown in Fig. 2. If a large CM artifact signal is coupled to the input of the AFE (V$_{\mathrm{in}}$ node in Fig. 1), the common-mode signal appears as it is, with only the DC level shifted to the tail current source drain voltage of the first-stage amplifier (G$_{\mathrm{M1}}$). This signal is then amplified by the following CMCL amplifier (A$_{\mathrm{CM}}$), and the result is applied back to the G$_{\mathrm{M1}}$ input through the capacitors (C$_{\mathrm{Acm}}$). Thus, the CMCL path operates as a negative-feedback loop from the perspective of the common-mode input. As a result, only a small error signal couples from the large common mode input to the first-stage amplifier thanks to the CMCL circuit. This operation can be expressed assuming that the output of the CMCL amplifier is not saturated;

(1)

$ \left(E_{CM}\frac{C_{IN}}{C_{Acm}}+V_{Acm}\right)\left(\frac{C_{Acm}}{C_{Acm}+C_{IN}}\right)=V_{IN,CM} $

Since the A$_{\mathrm{CM}}$ amplifier is not saturated, the V$_{\mathrm{Acm}}$ output can be shown as follows;

(2)

$ V_{Acm}=-E_{CM}\frac{C_{IN}}{C_{Acm}} $

Therefore, the CM error signal coupled into the first-stage amplifier becomes ideally 0. However, at this time, if C$_{\mathrm{Acm}}$ is smaller than C$_{\mathrm{in}}$ and a signal large enough to saturate the amplifier couples to the input, V$_{\mathrm{Acm}}$ is as follows:

(3)

$ V_{Acm}\neq -E_{CM}\frac{C_{IN}}{C_{Acm}} $

Therefore, a non-zero error signal enters the first-stage amplifier. In reference ^[10], resistors are used after the A$_{\mathrm{CM}}$, and thus the amount of the cancellation varies depending on the CM input frequency. However, using C$_{\mathrm{Acm}}$ instead of resistors in the proposed circuit allows the common-mode signal to be rejected according to the ratio of C$_{\mathrm{Acm}}$ to C$_{\mathrm{in}}$, and the signal is rejected with the same magnitude at all frequencies within the A$_{\mathrm{CM}}$ amplifier bandwidth. Considering the input noise degradation, the C$_{\mathrm{Acm}}$ was set to 8 pF, which is 80% of the 10 pF value of C$_{\mathrm{in}}$.

In addition, by using a comparator and logic circuits, the CMCL circuit switch automatically turns on when a large CM artifact is coupled to the input and turns off when a large CM input is not present, thus prevents the overall noise degradation under normal operations.

Fig. 2. Schematic of the proposed CMCL.

2. Narrow-band Buffer (NBB)

The proposed NBB schematic is shown in Fig. 3 and is designed using a current mirror OTA buffer. By increasing the width of the first-stage element of the current mirror and increasing the length of the second-stage element that copies the current, the second-stage current is lowered to several tens of pA, making the bandwidth very low. To adjust the low-pass filter bandwidth of the AFE with a 40-dB/dec slope, two NBB blocks are placed in series between the output of the LNA and the input of the PGA. In addition, a switch that directly connects the path between the LNA and the PGA allows the signal to pass without going through the NBB. To adjust the high-frequency bandwidth of the AFE, the NBB is placed in each feedback loop of the LNA and PGA. With all bandwidth adjustment switches turned off, it records signals within the 1 Hz to 10 kHz range, encompassing both LFP and AP signals. When only the low-pass bandwidth adjustment switch is turned on, it operates within the 1 Hz to 280 Hz range, recording only the LFP signal. When only the high-pass bandwidth adjustment switch is on, it operates within the 500 Hz to 10 kHz range, recording only the AP signal.

Fig. 3. Schematic of the proposed NBB.

3. Programmable Gain Amplifier (PGA)

The method of adjusting the gain in the PGA involves connecting switches and capacitors, thereby altering the capacitance value based on the ON/OFF state of the switch to achieve the desired gain. Among these methods, there are two approaches: one involves changing the input capacitor, which has the drawback of noise variation depending on the capacitor size. The other method involves adjusting the feedback capacitor, but it has the disadvantage of altering the low-pass cutoff frequency band whenever the gain changes. Therefore, in the proposed PGA, the gain is adjusted by varying the feedback capacitor, and both noise and bandwidth are designed to remain constant using the adaptive Miller compensation technique ^[12]. In Fig. 4, a cross-coupled capacitor structure is depicted, which is used in the feedback path of the PGA ^[2,13,14]. Using this method, the overall PGA feedback capacitance value can be expressed as:

(4)

$ C_{PGA,fb}=C_{1}+a_{1}C_{cross1}+a_{2}C_{cross2}+a_{3}C_{cross3} $

When capacitors are connected in parallel, $a_{1},$ $a_{2},$ and $a_{3}$ become +1, whereas when connected in a crossing manner, $a_{1},$ $a_{2},$ and $a_{3}$ become -1. The values of the capacitors are set as follows: $C_{PGA,fb}$ to 2~pF, and $C_{1}$, $C_{cross1}$, $C_{cross2}$, and $C_{cross3}$ to 1.1 pF, 500 fF, 300 fF and 100 fF respectively. The overall value of the feedback capacitance $C_{PGA,fb}$ varies according to the switching configuration, resulting in gains of 1, 2, 5, and 10 times.

In typical amplifiers, as the gain increases due to feedback, the bandwidth decreases. In other words, if the input capacitor is fixed and as the feedback capacitor decreases, the gain increases, leading to a reduction in bandwidth. To mitigate this issue, the method of using compensation capacitors to decrease the bandwidth for stability assurance in typical amplifiers is employed in reverse: as the gain increases, the compensation capacitors are decreased to maintain a consistent bandwidth. Therefore, the overall amplifier is designed to have a gain of 40 dB, 46 dB, 54 dB, and 60 dB, all resulting in a bandwidth of 1 Hz to 10 kHz.

Fig. 4. Schematic of the proposed cross-coupled capacitor used in the feedback path of the PGA.

III. Measurement Results

The proposed IC is fabricated using a 0.18-${\mu}$m CMOS process and Fig. 5 shows the chip micrograph of the overall AFE. The IC occupies an area of 0.48 mm$^{2}$ which includes an on-chip unity gain buffer for testing purposes. The IC is assembled on a FR4 PCB using chip-on-board packaging.

Fig. 6 shows the measured gain frequency response of the AFE while controlling the gain of the PGA. When the gain of the LNA is set at a fixed 40 dB and the gains of the PGA are tuned between 0 dB, 6 dB, 14 dB, and 20 dB, it can be observed that the AFE has a constant bandwidth of 1 Hz to 10 kHz. Fig. 7 shows the bandwidth-adjusted frequency response waveform by NBB. Fig. 8 shows the measured CMRR of the proposed amplifier, achieving over 85 dB in the main frequency band and over 110 dB near DC. Fig. 9 shows the measured input-referred noise (IRN) waveforms for the proposed amplifier's entire bandwidth (1 Hz to 10 kHz) in both ON and OFF states of the CMCL switch. The IRN due to the CMCL circuit is 3.29 ${\mu}$Vrms and 2.12 ${\mu}$Vrms for the ON and OFF states, respectively. A pre-recorded AP signal from a Sprague Dawley rat of the open source data set ^[15,16] is applied to the AFE input through a waveform generator for characterization and Fig. 10 shows the input and output waveforms which amplified the data at 40 dB setting. Fig. 11 shows the harmonic distortion waveforms while applying the differential input with 2 mVpp magnitude and 60 Hz frequency and the CM input with 1 Vpp magnitude and 2 kHz frequency. The intermodulation distortion caused by two signals of different frequencies is greatly reduced by the CMCL circuit. Also, the total harmonic distortion (THD) is -43 dB.

Table 1 shows a comparison of key performance metrics with previous papers. The proposed circuit offers flexibility in bandwidth and gain control and has good noise performance despite not employing chopper stabilization technology, which greatly reduces the overall circuit complexity of the AFE. Additionally, for less than 1% THD, the proposed amplifier can withstand up to 1 Vpp of CM artifact signal, which is the same magnitude as the supply voltage. It is important to note that some of the THD values in the comparison papers were either derived from simulation results ^[5] or were measurement results without inclusion of the CM signal ^[6,7], which resulted in superior THDs. Furthermore, due to the inclusion of the automatically operating CMCL circuit, additional PGA for gain control, and the use of NBB to adjust the signal bandwidth, the overall area of the proposed IC was slightly increased.

Fig. 5. Chip micrograph of the proposed AFE.

Fig. 6. Measured AC gain response of the AFE.

Fig. 7. Measured bandwidth response of AFE.

Fig. 8. Measured CMRR of the proposed amplifier.

Fig. 9. Measured input-referred noise with and without CMCL.

Fig. 10. Measured input (top plot) and output (bottom plot) pre-recorded AP signal waveform.

Fig. 11. Total harmonic distortion with and without CMCL.

IV. Conclusions

A low-power, low-noise, highly reconfigurable analog front-end IC is implemented using 180 nm CMOS process, capable of withstanding common-mode artifacts as large as 1 Vpp, equivalent to the supply voltage using the proposed common-mode cancellation scheme. Gain control and bandwidth control capabilities are possible, providing high flexibility to various neural signals with different amplitudes. The proposed AFE has a gain range of 40-60 dB, a minimum input-referred noise (IRN) of 2.12 ${\mu}$Vrms over 1 Hz - 10 kHz.