A 10 Gb/s MIPI D-PHY Receiver with Auto-skew Calibration Circuit using Random Data
SongChangmin1
JangYoung-Chan1,*
-
(Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi,
Gyungbuk, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Mobile industry processor interface, D-PHY, high-speed receiver, auto-skew calibration, random data, predetermined training data
I. Introduction
As mobile cameras and displays continue to improve in performance, such as resolution,
color depth, and frame rate, the speed of the interface for data transfer continues
to increase. The mobile industry processor interface (MIPI) D-PHY, which supports
both the camera serial interface (CSI) and display serial interface (DSI) protocols,
requires a circuit to compensate for the difference in latency between the data and
clock lanes as the data rate per lane increases [1,2]. For the MIPI D-PHY version 1.2, which provides data rates above 2.5 Gb/s, skew calibration
is supported to eliminate the difference in latency between lanes [3,4]. To eliminate time skew between data lanes and between data and clock lanes, predetermined
training data is defined in the MIPI D-PHY protocol, as shown in Fig. 1 [4]. The skew calibration presented in the MIPI D-PHY is initialized by a synchronous
sequence (16’hFFFF), which is performed using the same toggle pattern as the clock
lanes in the high-speed mode of the MIPI D-PHY. In this case, the minimum data length
of the toggle pattern is defined as 2$^{10}$ unit intervals (UIs), which is the minimum
data length of the toggle pattern. However, as the MIPI D-PHY is used in various applications,
arbitrary specifications outside of the protocol have been added by users. In particular,
modules or circuits, including lower versions of the MIPI D-PHY transmitters that
have already been developed, may not support the training data defined in the MIPI
D-PHY transmission protocol to eliminate time skew between data lanes and between
data and clock lanes.
In this work, an auto-skew calibration circuit is proposed for the MIPI D-PHY that
compensates the time skew between the four data lanes and between the data and clock
lanes using not only the predetermined training data but also random data not defined
in the MIPI D-PHY.
Fig. 1. Predetermined training data for skew calibration in MIPI D-PHY.
II. Design of 10 Gb/s MIPI D-PHY Receiver with Auto-skew Calibration
1. Proposed 10 Gb/s MIPI D-PHY Receiver with Auto-skew Calibration
The MIPI D-PHY receiver consists of four data lanes and one clock lane, as shown in
Fig. 2 [5-7]. Since the MIPI D-PHY receiver has four data lanes, it receives 2.5 Gb/s of data
per data lane to support a data rate of 10 Gb/s. Each lane consists of a high-speed
receiver (HSRX), a skew control block for controlling the delay line, and a step1
end detector to detect the end of the first operation of the auto-skew calibration
[8-11]. The HS$_{\mathrm{RX}}$ consists of a continuous time linear equalizer (CTLE), a
current mode logic (CML) buffer, and a level shifter (LS), as shown in Fig. 3, which is responsible for improving signal integrity due to channel loss and converting
analog level signals to CMOS levels. The CTLE, which performs equalization by source
degeneration, adjusts the strength of the equalization according to the loss of the
channel by controlling the degeneration associated with the source with a 4-bit binary
code. The signal with improved inter-symbol-interference (ISI) by the CTLE is amplified
by the CML buffer and converted to a CMOS level signal by the operation of the LS,
the last stage of the HS$_{\mathrm{RX}}$. Although the CTLE and CML output signals
with relatively low common mode due to the use of input stages with PMOS transistors,
the LS uses NMOS transistors for its input stage. This is to reduce the increase in
power consumption caused by the absence of a tail current source in the LS.
The proposed auto-skew calibration is performed by using the data skew control and
delay line blocks of each data lane, the clock skew control and delay line blocks
of the clock lane, and the step1 end detector block. As shown in Fig. 4(a), a time skew between the data and the clock can cause errors in the interface of
the MIPI D-PHY using the source synchronous clock scheme when the rising and falling
edges of the received clock are not centered on the received data. In this case, the
proposed auto-skew calibration compensates the time skew between the four data lanes
and between the data and clock lanes by the following three processes. On the other
hand, according to the specification of MIPI D-PHY, the time skew between data and
clock of each data lane is required to be kept less than 0.5 UI). The first calibration
process aligns the edges of the data to the rising edge of the clock, as shown in
Fig. 4(b). This process first removes the time skew between the four data lanes, which is performed
by adjusting the time delay of the four data through control of the delay line of
each data lane, without controlling the delay time for the clock signal. When this
process is complete in each data lane, the step1 end detector detects this and supplies
the S1$_{\mathrm{END}}$ signal to the clock lane to proceed to the next step. Fig. 4(c) shows the second process for the proposed auto-skew calibration. By comparing the
two phases of the input and output signals of the delay line located in the clock
lane, the control code for a time delay corresponding to half a cycle of the clock
signal is determined. The final process sets the two edges of the clock to be the
center of the data, as shown in Fig. 4(d), which is performed by setting the control code for the delay line of the clock determined
in the process in Fig. 4(c) to half.
Fig. 2. Block diagram of proposed MIPI D-PHY.
Fig. 3. Circuit diagrams of HSRX: (a) CTLE; (b) CML buffer; (c) LS.
Fig. 4. Auto-skew calibration sequence: (a) initial condition; (b) data alignment
of data to CKQ; (c) detection of half cycles of CKQ; (d) optimization of delay control
for CKQ.
2. Proposed Auto-skew Calibration using Random Data
A simple block diagram of the proposed auto-skew calibration is shown in Fig. 5(a). The delay line, which is used to delay the data and clock for the auto-skew calibration,
uses 32 delay cells consisting of three NANDs and is controlled by a 32-bit one-hot
code [12]. This structure reduces power consumption by disabling all cells other than those
activated by a given path. The first process of the proposed auto-skew calibration,
which is a three-step process, is performed by phase comparison in the data skew control
block of each data lane and time delay control in the Delay Line. A sense amplifier
flip-flop (SAFF) based phase detector [13,14] located in the data skew control block of each data lane compares the phases of the
clock and data to each other. To implement the auto-skew calibration even for random
input data including the predetermined training data in the form of toggles, the signal
generated by the rising edge of the input data, not the clock signal, is used as the
synchronization signal for the phase detector in each data lane. Because the MIPI
D-PHY uses double data rate signaling, the rising edge of the input data can occur
while the clock is both high and low. When the predetermined training data of the
MIPI D-PHY is input, the clock signal is continuously sampled by the input data once
per cycle and its phase can be compared because the input data is a toggle signal
with the same frequency as the clock signal. However, since the random input data
is not a periodic signal and its period is not defined, it is not possible to determine
the phase relationship of the two signals by comparing their phase with the clock
at each rising edge of the random input data. Therefore, in this work, the RDQ signal
generated from the rising edge of the data when the clock is only low is used as the
synchronization signal for the phase detector for skew calibration by performing a
continuous phase comparison of the two signals, as shown in Fig. 5(a). In the first process of the proposed auto-skew calibration, the edges of the data
and the edges of the clock are aligned when the result of the phase detection is a
transition from a value of 0 to a value of 1, as shown in Fig. 5(b). The RD is generated as a short pulse on the rising edge of the DQ#, the output of
the delay line of each data lane, and the RDQ is generated by the AND operation of
the RD with the /CKQ, the output of the delay line of the clock lane. In other words,
the RDQ is the signal generated by the rising edge of the data input while the clock
is low.
On the other hand, if the RDQ is generated by a short pulse signal with a very small
high width, such as glitch noise, the phase detector may not be able to perform the
phase comparison of the two input signals normally, i.e., a dead zone of the phase
detector may occur. In this work, to eliminate the dead zone in the phase detection
of clock and data, the phase detection is performed on the rising edge of the RDIN,
which is generated by delaying the RDQ by a certain amount of time (${\alpha}$). When
the CKQ is synchronized to the RDIN and sampled high, the delay control of the data
of each data lane is terminated. The time delay code of the data determined in this
process is updated with the value added by the code value (${\alpha}$) used in the
replica delay line (RDL), as shown in Fig. 5(b). This updated value is finally determined as the time delay code and fed to the delay
line for the data. The phase detection and the update of the time delay code for the
delay line are performed every 8 cycles of the RDQ. This is to ensure the stabilization
of the delay line when updating the code. When the data delay adjustment of each data
lane is complete, the D#$_{\mathrm{END}}$ signal is generated. Also, when the data
delay adjustment of all data lanes is complete, the S1$_{\mathrm{END}}$ signal is
activated by the step1 end detector and fed to the clock skew control block of the
clock lane as an indicator for the next process of the proposed auto-skew calibration.
The second process of the proposed auto-skew calibration is performed in the clock
lane. Since the MIPI D-PHY uses double data rate signaling, the time margin is optimized
by centering the rising and falling edges of the clock on the aligned data. Therefore,
the time skew between data and clock can be optimized by setting the time delay of
the clock to a value equal to 1/4 of its period. This method can be implemented with
less hardware than the conventional scheme [8] where the clock scans the data of 1-UI to find the delay of the clock. First, the
phases of the input (CK$_{\mathrm{PRE}}$) and output (CKQ) of the delay line located
on the clock lane are compared to each other to detect the time delay equivalent to
a clock half cycle. When the resulting value of the phase detector transitions from
0 to 1 as the control code on the delay line for the clock is incremented, the time
delay value for the clock half cycle is stored in a 5-bit counter. Then, the value
stored in the 5-bit counter divided by 2 is set as the control code of the time delay
of the delay line for the clock. Thus, the edge of the clock is positioned in the
center of the aligned data in the first process of the proposed auto-skew calibration.
The skew calibration process illustrated in Fig. 5(b) is for the case where the low of the clock is sampled with the rising edge of the
random data input to the receiver at the start of the auto-skew calibration. The proposed
auto-skew calibration also allows skew calibration to be performed in the reverse
case. The flow chart of the proposed auto-skew calibration based on the initial clock
and data state is shown in Fig. 6. At the beginning of the proposed auto-skew calibration, if the rising edge of the
random data input is sampling the high of the clock, the delay line of the data is
increased until the low of the clock is sampled. After that, the proposed auto-skew
calibration process proceeds the same as the process described in Fig. 5(b).
According to the MIPI D-PHY version 1.2, the skew calibration is performed using the
predetermined training data in the form of toggles that is supplied for a period of
time after the high-speed mode is started. Therefore, this skew correction can usually
be performed in the initial situation of the system. On the other hand, the proposed
auto-skew calibration is performed on any random data, including the predetermined
training data, and is therefore applicable to all versions of the MIPI D-PHY. It can
also perform foreground skew calibration as well as background calibration in situations
where real data is received.
Fig. 5. Proposed auto-skew calibration: (a) block diagram; (b) timing diagram.
III. Simulation Results of Proposed MIPI D-PHY Receiver with Auto-skew Calibration
The proposed MIPI D-PHY receiver was designed by using a 28-nm CMOS process with a
supply voltage of 1.0 V. The HS$_{\mathrm{RX}}$ consumes 0.4 mW/Gbps of power per
lane.
At a data rate of 2.5 Gbps, the CTLE, CML, and LS of the HS$_{\mathrm{RX}}$ consume
0.26 mW, 0.38 mW, and 0.40 mW, respectively, resulting in a power consumption of 1.04~mW
for the HS$_{\mathrm{RX}}$. For the simulations to evaluate the receiver and auto-skew
calibration of the designed MIPI D-PHY, a channel with a length of 130 cm on an FR-4
printed circuit board was used. The channel has a frequency response characteristic
of -17 dB at 1.25 GHz and -31.2 dB at 2.5 GHz. Fig. 7 shows the frequency response of the CTLE shown in Fig. 3(a) by HSPICE in a typical process and temperature of 25 $^{\circ}$C. It has a peak voltage
gain at 1.25 GHz, and the DC gain varies between 1 dB and 11 dB. Fig. 8 shows the simulated high-speed performance of the designed HS$_{\mathrm{RX}}$. When
the received input data with a data rate of 2.5 Gb/s/lane has a peak-to-peak time
jitter of 109 ps, the output signals of the CTLE, CML, and LS have a peak-to-peak
time jitter of 27.7 ps, 29.1 ps, and 45.8 ps, respectively, and the output signal
of the delay line has a peak-to-peak time jitter of 43.3 ps. The first stage of HS$_{\mathrm{RX}}$,
CTLE, reduces the ISI of the input signal coming into the MIPI D-PHY high-speed receiver,
which improves the time jitter of the received signal. The signal was then amplified
to CMOS level by the LS, which slightly increased the time jitter, but did not increase
the time jitter in the delay line used in the proposed auto-skew calibration process.
This confirms that the band-width of the data line is designed to be larger than the
bandwidth of the HS$_{\mathrm{RX}}$, which will not worsen the overall high-speed
characteristics of the MIPI D-PHY receiver.
Fig. 9 shows the simulation results of the Delay Line used in the proposed auto-skew calibration
for process, voltage, and temperature (PVT) variations. Where SS means that the process
is slow for both NMOSFETs and PMOSFETs, with a supply voltage of 0.9 V and a temperature
of 125$^{\circ}$C. TT means the process is typical, with a supply voltage and temperature
of 1.0 V and 25$^{\circ}$C, respectively, and FF means the process is fast, with a
supply voltage and temperature of 1.1 V and ${-}$40$^{\circ}$C, respectively. Also,
SF means a slow corner process for NMOSFETs and a fast corner process for PMOSFETs.
FS is the complete opposite. For the simulation condition of TT, the time resolution
due to the change of the control code of the delay line has a range of 16.4 ps to
19.6 ps, with an average value of approximately 18.7 ps, as shown in Fig. 9(a). Also, the average value of the duty cycle ratio of the output signal of the Delay
Line is approximately 50.2%, as shown in Fig. 9(b). Fig. 9(c) shows that the time delay of the Delay Line is varied in the range of 20.3 ps to
1177.3 ps by a binary code of 5 bits in the same conditions. In order to perform auto-skew
calibration at a data rate of 2.5 Gb/s/lane in this work, the Delay Line is designed
to allow time delay control of more than 2 UIs, i.e., 800 ps, in the simulation condition
of FF with the smallest time delay.
Fig. 10 shows the results of a simulation of the proposed auto-skew calibration using the
predetermined training data supported by the MIPI D-PHY version 1.2. Before the calibration,
the data skew was set to 230 ps, the setup time to 87 ps, and the hold time to 83
ps. After the first process of the proposed auto-skew calibration, the time skew between
the four data was reduced to 18 ps. And after the second process, the clock was located
at the center of the data aligned in the first process, resulting in a setup time
of 195 ps and a hold time of 186 ps. Fig. 11 shows the results of a simulation on the performance of the proposed auto-skew calibration
on random input data. The random data used in this simulation was supplied from a
pseudo-random bit sequence generator implemented by using a serial linear feedback
shift register with a polynomial of x$^{23}$ + x$^{18}$ + 1. Similar to the results
in Fig. 10, the proposed auto-skew calibration improved the data skew, setup time, and hold
time to 19 ps, 196 ps, and 186 ps, respectively. The delay line used for the au-to-skew
calibration consumes 1.41 mW of power at maximum delay for a signal with a frequency
of 1.25 GHz.
Fig. 12 shows the characteristics of the proposed auto-skew calibration for PVT variations.
As shown in the simulation results shown in Fig. 9, the representation of TT, SS, and FF includes variations in process, supply voltage,
and temperature. Fig. 12(a) and (b) are the simulation results for the proposed auto-skew calibration using the predetermined
training data, where the calibrated data skew is reduced to 0.05 UI or less in the
simulation conditions of TT and FF. For the simulation of SS condition, it is slightly
larger than 0.1 UI, which is due to the increased time delay for each control code
in the delay line. The setup and hold time margins also improved from 0.42 UI to 0.49
UI for the three simulation conditions. The improvement of the setup and hold time
margins as well as the data skew by performing the proposed auto-skew calibration
shows similar results for the case of using the random data, as shown in Fig. 12(c) and (d).
Table 1 compares the characteristics of published parallel interfaces for main memory DRAMs
and the MIPI D-PHY V2.0 with those of the interface circuit that includes the auto-skew
calibration proposed in this work. While the interface circuits published in the two
prior literature require toggle data to be received to calibrate time skew, the proposed
auto-skew calibration does not require any special input signal, i.e., it supports
time skew calibration for random input data including toggle input data.
Fig. 6. Flow chart of proposed auto-skew calibration.
Fig. 7. Frequency response of designed CTLE.
Fig. 8. Simulation results high-speed receiver: (a) input data; (b) output of CTLE;
(c) output of CML; (d) output of LS; (e) output of Delay Line.
Fig. 9. Simulation results Delay Line: (a) resolution of time delay; (b) duty cycle
ratio; (c) total time delay.
Fig. 10. Auto-skew calibration simulation results using training data: (a) before
calibration; (b) after calibration.
Fig. 11. Auto-skew calibration simulation results using random data: (a) before calibration;
(b) after calibration.
Fig. 12. Auto-skew calibration results according to simulation condition: (a) data
skew in case of using training data; (b) setup and hold time margins in case of using
training data; (c) data skew in case of using random data; (d) setup and hold time
margins in case of using random data.
Table 1. Comparison of parallel interface between DRAM and MIPI D-PHY interfaces
|
Reference
|
ASSCC 2018 [15]
|
TCE 2019
[5]
|
This work
|
|
Application
|
DRAM
|
MIPI D-PHY v2.0
|
MIPI D-PHY v1.2
|
|
Technology
|
20 nm CMOS
|
110 nm CMOS
|
28 nm CMOS
|
|
Supply voltage
|
1.0
|
1.2
|
1.0
|
|
Data rate
|
3.2 Gbps/pin
|
5.0 Gbps/lane
|
2.5 Gbps/lane
|
|
Skew
calibration type
|
DLL based
|
1-UI scan
|
1-UI scan
|
|
Signal type for calibration
|
toggle data
|
toggle data
|
random data, toggle rata
|
|
Peak-to-peak jitter of receiver (ps)
|
58.89
@ 3.2 Gb/s*
|
50
@ 5Gb/s*
|
43.3
@ 2.5 Gb/s**
|
|
Power of receiver
(mW/Gbps/lane)
|
-
|
5.6
|
0.4
|
*measured results, **simulated results
IV. Conclusions
The proposed MIPI D-PHY receiver, which is designed by using a 28-nm CMOS process
with a supply voltage of 1.0 V, consists of 4 data lanes and 1 clock lane sup-porting
2.5 Gbps per lane, with a total data rate of 10 Gbps. In order to support the skew
calibration function in all versions of the MIPI D-PHY, the auto-skew calibration
circuit was proposed for the MIPI D-PHY high-speed receiver to support skew calibration
for random input data as well as the predetermined training data for the MIPI D-PHY.
The proposed auto-skew calibration improved the data skew, setup time, and hold time
to 19 ps, 196 ps, and 186 ps, respectively.
ACKNOWLEDGMENTS
This work was supported by the Grand Information Technology Research Center Program
(IITP-2024-2020-0-01612, 50%) and the ITRC support program (IITP-2024-RS-2024-00438288,
50%) through the IITP funded by the MSIT, Republic of Korea. The EDA tool was supported
by the IC Design Education Center, Republic of Korea.
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Changmin Song received the B.S. and M.S. degrees from the Department of Electronic
Engi-neering, Kumoh National Institute of Technology, Gumi, South Korea, in 2019 and
2021, respectively. Since 2021, He is currently a Ph.D. candidate. His research interests
include high speed multi-level transceiver, SerDes, phase-locked loop, clock and data
recovery.
Young-Chan Jang received the B.S. degree in the department of elec-tronic engineering
from Kyungpook National University, Daegu, Korea, in 1999 and the M.S. and Ph.D. degrees
in electronic engineering from Pohang University of Science and Technology (POSTECH),
Pohang, Korea, in 2001 and 2005, respectively. From 2005 to 2009, he was a Senior
Engineer in the Memory Division, Samsung Electronics, Hwasung, Korea, working on high-speed
interface circuit design and next-generation DRAM. In 2009, he joined the School of
Electronic Engineering, Kumoh National Institute of Technology, Gumi, Korea, as a
Faculty Member, where he is currently Professor. His current research area is high-performance
mixed-mode circuit design for VLSI systems such as high-performance signaling, clock
generation, and analog-to-digital conversion.