I. Introduction

Deep neural networks (DNNs) are increasingly used in safety-critical disciplines like automotive ^[1] and aerospace ^[2], where dependability is paramount due to the potential dire consequences of failures, such as loss of human life or significant environmental harm. Among dependability attributes, lifetime resilience ^[3] emerges as a primary concern of intelligent edge devices in safety-critical applications, demanding particular attention. Meanwhile, the ever-increasing complexity of DNN models poses challenges on edge devices with limited resources. Thereby, the primary focus of previous research on DNN deployment has been enhancing computation efficiency, such as through compression and quantization which reduces error resilience of special-purpose accelerators by intrinsic redundancy elimination ^[4,5].

Whereas continuous scaling of CMOS technology feature size has introduced high-performance and computation-efficient processing platforms, it has significantly threatened the lifetime resilience of modern DNN inference engines, primarily due to aging factors. Bias Temperature Instability (BTI), including NBTI and PBTI, stands out as a dominant aging factor in advanced CMOS technologies ^[6,7]. BTI causes timing degradation through continual electrical stress on transistors, leading to performance reduction, timing errors, and eventual lifetime loss. Various operational parameters such as temperature, voltage, and stress affect BTI degradation ^[8,9]. The conventional method of conservative guard banding appears insufficient for modern hardware accelerators due to performance loss by considering more than 20% safety margin over the lifetime ^[10]. Nonetheless, state-of-the-art research focuses on enhancing the lifetime of DNN accelerators through approximation techniques and temperature mitigation, but with a slight reduction in accuracy ^[11]. Other leading research efforts have attempted to extend the lifetime of DNN accelerators by reducing stress in activation and weight memories using aging-aware data encoding ^[12], iterative power gating, and memory bank switching techniques ^[13]. Conversely, the appropriate data representation became an important research direction in designing DNN accelerators ^[18]. Conventional number systems appear suboptimal for the design of specialized DNN accelerators. Previously, diverse alternative number systems have been explored in DNN accelerators ^[17].

This research investigates aging mitigation for lifetime resilience enhancement by reducing stress and increasing redundancies through employing Redundant Number System (RDNS) ^[19]. Adapting RDNS for DNN acceleration, we have a serious obstacle of redundancies and overheads arising from computing in RDNS. To manage the overheads, we propose the Binary Signed Digit (BSD)-serial processing over bit-serial processing elements in the conventional binary number system (BNS) ^[14-16]. In brief, serial processing can increase efficiency through 1) dynamic precision adjustment, 2) computation active pruning, and 3) circuit design simplification.

Overall, we focus on combining the concepts of (a) serial processing and (b) computing in RDNS to evaluate their collaborative impact on improving the lifetime resilience of DNN accelerators. Herein, we evaluate the lifetime of BSD-serial PEs compared to conventional bit-serial PEs operating in the BNS. Based on the literature, execution elements are among the most timing-critical units for evaluating the overall lifetime of a processor. ^[20]. To clarify the RDNS computing effectiveness for lifetime extension, we have used a cross-layer workflow to evaluate BTI in the data path of the DNN accelerator. The proposed approach jointly exploits input (activation and weight) and number-system impacts on lifetime resilience. Experimental results demonstrate the proposed design can improve lifetime resilience, via stress and degradation mitigation, while conserving computational efficiency. Computing in RDNS can efficiently address the strict lifetime constraints of safety-critical disciplines.

The major contributions can be summarized as:

1) For the first time, we explored number-system and workload effects on BTI stress of accelerators data path. Computing in RDNS contributes to 36% lower stress on average for diverse workloads.

2) We evaluated the lifetime of PEs considering all affecting factors, i.e., stress, temperature, and voltage variations. BSD-serial processing causes an average 35.5% higher lifetime in MTTF (mean time to failure) compared to the baseline.

3) We introduced a cross-layer workflow to evaluate aging in the DNN accelerator data path.

The rest of this paper is organized as follows. Section II presents the preliminaries. The proposed RDNS-based processing approach is overviewed in Section III. Section IV clarifies the detailed architecture of processing elements. Section V presents the experimental results and comparison over the baseline. Finally, Section VI concludes the paper.

II. Background

In PMOS transistors, NBTI results in the threshold voltage shift increasing the critical path delays and eventually causing timing errors. NBTI occurs when the PMOS transistors are under stress with negative voltage bias ($V_{GS}=-V_{dd}$). Two major theories for the NBTI process explanation are reaction-diffusion (RD) and trapping/de-trapping (TD) models ^[8]. Both models explain NBTI as a 2-stage process including stress and recovery phases. The long-term NBTI degradation model based on RD theory is described by ^[21]:

where A depends on operational parameters such as temperature ($T$) and voltage ($V_{dd}$), $K$ is a fitting parameter, $Y$ is stress, $t$ is service time and n is assumed between $1/4$ and $1/6$ depending on the diffusing species ^[21]. In this work, we use RD for NBTI aging evaluation using $n=1/6$. According to ^[22], $A\left(T,\,\,V_{dd}\right)$ can be calculated as:

where $t_{ox}$ is the effective oxide thickness and KB is the Boltzmann constant $(8.6\times 10-5eV/K),$ while $E_{0}=0.1897eV$and $B=0.075eV\,nm/V$ are fitting parameters. As seen, the main workload factor in NBTI aging is stress which can be evaluated by internal nodes’ duty cycles or signal probability ($SP$). For PBTI, $SP$ is the ratio of the time with logic one at a gate input to total service time, while the probability of 0’s determines the NBTI-induced degradation in PMOS devices. Thus, both $SP$ and $1-SP$ are important to cover both NBTI and PBTI. These factors are given to the model to estimate the delay degradation.

Also, the operating temperature of a chip can be calculated from ^[23]:

where $T_{chip}$ is the average temperature, $T_{a}$ is the ambient temperature ($T_{a}=25^{\circ}C$), $P_{tot}$ is the total power consumption, A (in $cm^{2}$) is the chip area, and $R_{\theta }$ is the equivalent thermal resistance.

In this study, lifetime is defined and estimated as a period in which $\Delta V_{th}$ reaches to 10% of the initial nominal value ^[24].

III. BSD-serial Processing Approach

The target operation of PEs can be described by $\sum _{i=0}^{l-1}W_{i}\times A_{i}$, where $W_{i}$ and $A_{i}$ represent weights and activations, respectively. Binary serial PE is the baseline of this study as conventional Bit-serial. Compared to fix-precision PEs, serial processing can improve performance by 2.33X on average via on-the-fly per-layer bit precision adjustment ^[14]. Here, activations and weights arrive in binary bit-serial and bit-parallel, respectively. In each cycle, a bit column of input activations is bitwise ANDed by corresponding parallel weight bits to produce partial products. Then, partial products are fed to a compressor to generate the sum of products. Fig. 1(a) shows the computing approach of conventional bit-serial architecture. Serial engine process inputs in p-cycle length loops, where $p$ is the activations precision in bits. In the first cycle of a loop, MSB bit of $l$ concurrent input activations are ANDed, which produce $l$ p-bit terms. The compressor sums these terms into a partial sum using an adder tree. For the remaining $p-1$ cycles of a phase, the accumulator shifts the previous residual by one bit, while accumulating the new some of the product. According to Fig. 1(b), the processing approach of BSD-serial PE is like Bit-serial while replacing BNS with RDNS in input activations, partial products, partial sums, and generated output. Herein, we keep radix = 2 with the corresponding redundant digit set $\left\{-1,0,1\right\}$. In this regard, a digit is represented with a couple of positive and negative bits with 0 or 1 and -1 or 0 arithmetic values, respectively. For example, $N~ =~ +11$ can be represented as $1011$ or $110\overline{1}$, where in Positive/ Negative representation, it reads as ($N+=1011,$ $N-=1111$ or $N+=1100,$ $N-=1110$).

The BSD-serial processing approach performs inference with a minimized latency (or maximized frequency) independent of weight bit-precision, based on limited carry propagation in RDNS adders. Fig. 2 illustrates an N-digit RDNS adder, featuring an overall architecture similar to carry-save addition.

Fig. 1. Different processing approaches in accelerator PEs: (a) BNS Bit-serial; (b) RDNS BSD-serial.

Fig. 2. N-digit RDNS adder based on carry-save addition.

IV. Detailed Design of PEs

BSD-serial PE architecture is composed of 3 main subunits including an RDNS partial product generator (R-PPG), an RDNS compressor (R-C), and an RDNS accumulator (R-AC). Fig. 3 illustrates the overall BSD-serial architecture extending binary bit-serial PE to RDNS with 16-bit precision activation and weight inputs. Activations arrive in RDNS while weights are in binary 2’s complement. In R-C and R-A, binary adders are replaced with Carry save adders which can decrease the latency by eliminating Carry propagation. The R-PPG gets 16${\times}$16-bit synapse weights in binary and 16 BSD-serial activations. The R-PPG generates 16 partial products each in 16-BSD, feeding the R-C in $X_{0}$ to $X_{15}$ inputs to generate compressed partial sum output. R-AC operates in 16-cycle loops, starting with 0 residual, and accumulates compressed partial sums produced by R-C.

Fig. 3. Overall BSD-Serial PE Architecture.

Fig. 4 summarizes the proposed cross-layer workflow including required tasks in different layers for lifetime evaluation. In this context, we first describe the Bit-serial and BSD-serial architectures in RTL and synthesize them using a 28 nm cell library and 0.9 V nominal voltage to produce the netlist and standard delay format (SDF) files. Table 1 demonstrates an overview of generated reports by the Design Compiler synthesis tool. In parallel, different DNN models e.g., ResNet18 on the ImageNet dataset, are deployed in Python to profile evaluation benchmarks including weights and activations. Next, post-synthesis cycle-accurate simulations are conducted on benchmarks to produce timing reports and value change dump (VCD) outputs. Then, VCDs are explored to generate power and stress (signal probability) reports using a power analysis (Primetime) tool. After that, the maximum temperature is estimated based on previously measured power and area and using the Hotspot tool based on Eq. (3). Finally, we used Matlab to predict degradation and lifetime for different architectures and workloads considering all factors.

Fig. 4. The proposed cross-layer evaluation workflow.

This workflow is cross-layer because it analyzes interactions across multiple layers. It mainly differs from conventional ASIC design flows because it adds BTI stress estimation and lifetime prediction tasks. In this study, Lenet5 is utilized on the MNIST dataset for the primary evaluation. VGG16 and ResNet18 are applied to the ImageNet dataset for supplementary evaluation and to extend the experimental results.

1. Experimental Results

In this section, we will initially evaluate the impacts of architecture and number-system effects on the internal stress of the PEs while running different DNN models. Fig. 5 illustrates the histogram of the stress ($SP$) variations for the target designs running different DNNs. We can see that by computing in RDNS, the stress (and recovery) phases have become more balanced. Moreover, average stress variations among 16 different filters of ResNet18 for 10 different input images are illustrated in Fig. 6. Accordingly, on average BSD-serial architecture represents 36% lower stress compared to conventional Bit-serial PE. As mentioned, both $SP$ and $1-SP$ are considered for comparison.

Next, the efficacy of considering stress in aging and lifetime estimation is explored over bit-serial and BSD-serial designs. For the sake of clarity, we have calculated the $\mathrm{V}_{\mathrm{th}}$ degradation for successive runs of LeNet5, VGG16, and ResNet18 on introduced PEs. We assumed the worst-case temperature and fixed $V_{dd}$ among PE matrices. In this regard, only stress varies a long DNN executions. According to synthesis results, the temperature is almost equal between Bit-serial and BSD-serial designs because the area and power almost equal increase considering (3). Fig. 7 illustrates NBTI-induced aging degradation when running different DNNs, in the form of $\mathrm{V}_{\mathrm{th}}$ shift, which starts from 0 and increases up to 0.03 V (10% of initial value). Moreover, Fig. 8 illustrates the lifetime improvement in MTTF considering stress variations among different designs. As seen, the BSD-serial design extends the lifetime by 35.5% compared to the baseline Bit-serial due to balancing BTI stress.

Fig. 5. The histograms of stress variations among architectures running LeNet5, VGG16 (MNIST) and ResNet18 (ImageNet).

Fig. 6. BTI stress variations among different architectures, filters, and input images running ResNet-18.

Fig. 7. NBTI degradation in target architectures running different DNN filters considering stress variations.

Fig. 8. Lifetime comparison among designs running LeNet5, VGG16, and ResNet18 filters considering stress variations.

VI. Conclusion

Hardware accelerators have shown high computation efficiency, making them the first choice for DNN acceleration on edge devices. Considering processing elements (PEs) array as the heart of DNN accelerators with multiply-accumulate functionality, this research combines computing in RDNS with a serial processing approach to extend the lifetime resilience, investigating the BTI stress variations on the accelerator’s data path. The proposed technique extended the lifetime by 35.5% compared to conventional bit-serial PE by 36% reducing the stress on average.

For future research, we aim to extend computing in RDNS to emerging DNN accelerators with systolic array architecture to improve lifetime resilience. Additionally, we will explore operating voltage scaling, leveraging performance gained by computing in RDNS to further improve lifetime resilience, and apply the BSD-serial computing concept to systolic array-based DNN accelerators. Ultimately, we intend to expand the RDNS capability in lifetime extension to support training and inference computing phases.