1. Operation Description of the Proposed SCR

Fig. 1 shows the cross sections of the LVTSCR, LTDDSCR, and proposed devices. The proposed structure was designed based on LVTSCR and LTDDSCR; thus, traditional LVTSCR and LTDDSCR devices were utilized to verify its physical mechanisms and electrical properties. In LVTSCR, a GGNMOS structure was inserted into a general SCR, thereby minimizing the base region of the NPN parasitic bipolar transistor in the gate region while enabling low trigger voltages ^[12]. LTDDSCR forms a general SCR with a symmetrical structure and the same discharge path for negative and positive ESD surges ^[13]. In addition, it lowers the trigger voltage by including a P+ bridge region. Further, LTDDSCR exhibits a longer current path than LVTSCR; thus, it exhibits high dynamic resistance. Moreover, it can provide bi-directional discharge characteristics through a symmetrical structure. However, both LVTSCR and LTDDSCR do not possess structural features required for holding voltage engineering or other latch-up immunity, and the holding voltage must be controlled through the traditional length increasing method. Therefore, it occupies a very large area to be applied to an actual high voltage IC. In contrast, the proposed protection device included a P+ bridge region similar to that in LTDDSCR. In addition, it incorporated an NMOS structure similar to that LVTSCR, and electrically connected the P-drift bridge and N+ diffusion region, thereby forming a symmetrical structure. Fig. 1(c) shows the cross section of the proposed device and its equivalent circuit. Upon the application of a positive ESD surge to PAD_A of the proposed device, the P-drift and N-well junction become forward biased and the potential of the N-well increased. When the electric field reached the threshold, an avalanche breakdown occurred at the boundary of the right P+ bridge region. Further, in the generated electron hole pairs (EHP), the hole current flowed to PAD_B through the P-well region and increased the potential of the P-well. Because of this phenomenon, the N+ diffusion region and forward diode were turned on. Consequently, the parasitic bipolar NPN transistor (Q$_{\mathrm{N2}}$) began operations and the electron current flowing through Q$_{\mathrm{N2}}$provided the base current of the parasitic bipolar PNP transistor (Q$_{\mathrm{P}}$), thereby operating Q$_{\mathrm{P}}$ and forming an SCR-positive feedback loop. Here, the increased potential of the P+ bridge region was electrically connected to the drain of the inserted MOSFET to operate the additional bipolar transistor (Q$_{\mathrm{N4}}$). Subsequently, Q$_{\mathrm{N4}}$ partially discharged the collector current of Q$_{\mathrm{N2}}$ flowing into the base region of Q$_{\mathrm{P}}$, thus reducing the loop gain. Therefore, the proposed structure can effectively exhibit a high holding voltage. Moreover, as it has a symmetrical structure, Q$_{\mathrm{N1}}$, Q$_{\mathrm{N3}}$, and Q$_{\mathrm{P}}$ can operate with the identical functions even when a positive ESD surge is applied to PAD_B.

Fig. 1. Cross sections of the (a) low voltage triggering SCR (LVTSCR); (b) low trigger dual-directional SCR (LTDDSCR); (c) the proposed SCR structure.

2. Two-dimentional TCAD Simulation Results

This study conducted a two-dimensional technology computer-aided design (TCAD) simulation to verify the operating principles and mechanism of the proposed device ^[14,15]. Fig. 2 shows the cross-sectional view realized via a TCAD simulation of the experimental devices LVTSCR, LTDDSCR, and the proposed protection device. The mesh factor was set to become increasingly denser as it approached the junction. The impact ionization simulation results of each experimental device are shown in Fig. 3. In this experiment, input voltage was applied to PAD_A (anode), and PAD_B (cathode) was grounded. As shown in Fig. 3(a) and (b), where impact ionization occurs only at the well junction where avalanche breakdown occurs in Fig. 3(a) and (b), the conventional LVTSCR and LTDDSCR exhibit high levels of impact ionization. On the other hand, in the proposed device in Fig. 3(c), additional impact ionization was observed on the drain of the MOSFET (red square) formed in the P-well region, thus confirming the additional operation of Q$_{\mathrm{N4}}$

Fig. 2. Cross-section of experimental devices realized by TCAD simulation for (a) LVTSCR; (b) LTDDSCR; (c) proposed device.

Fig. 3. Cross section where impact ionization simulation was performed for (a) LVTSCR; (b) LTDDSCR; (c) the proposed device.

Fig. 4. Mixed-mode simulation results waveform for HBM 4 kV and hole potential signed log (after triggering): (a, b) LVTSCR; (c, d) LTDDSCR; (e, f) proposed device.

Fig. 5. Cross section where total current flow line simulation was performed for (a) LVTSCR; (b) LTDDSCR; (c) proposed DDSCR.

Further, a mixed-mode simulation was performed to verify the operating principle and effect of the proposed device ^[16,17]. In this experiment, all devices were set to the same width, and a virtual circuit composed of a 1.5k${\Omega}$ resistor and a 100 pf capacitor applied 4 kV of the human body model (HBM) to each test device ^[18]. The snapback waveform and lattice temperature were compared as in Fig. 4(a), (c) and (e). The simulation results indicate the that the proposed device performed a triggering operation at a relatively high level voltage and exhibited an improved snapback waveform compared to general LVTSCR and LTDDSCR. The cause of these experimental results can be confirmed based on the hole potential simulation results at the time after the device of Fig. 4(b), (d) and (f) of Q$_{\mathrm{N4}}$ was turned on.

In the conventional LVTSCR and LTDDSCR in Fig. 4(b) and (d), a high level of hole potential was observed only in the P-well region adjacent to the input, whereas in the proposed device in Fig. 4(f), a significant level of hall current was observed in the base region of Q$_{\mathrm{N4}}$ (red dotted circle). Thus, Q$_{\mathrm{N4}}$ continued to operate and still reduced the SCR loop gain after the device is fully turned-on. Therefore, the proposed device exhibited a high holding voltage owing to its structural characteristics.

Fig. 5 presents the total current flow of the LVTSCR, LTDDSCR, and the proposed SCR in before triggering, at the point of triggering, and after the fully turn-on in sequence. Contrary to the LVTSCR and LTDDSCR, where dense lines are formed from the substrate towards the surface, the current paths of the proposed device are unfolded asymmetrically through the center N-well at the trigger point due to Operation of additional NPN bipolar transistor (Q$_{\mathrm{N4}}$). In the triggering point, a current flow line is formed between the drain and source regions of Q$_{\mathrm{N4}}$. In the fully turned-on state, Q$_{\mathrm{N4}}$ remains turned on, a current path bypassing towards the substrate, forms at the bottom of the gate.

1. Comparison with Conventional Structures

The LVTSCR and LTDDSCR, which were used for comparison, were fabricated with the same width of 80 ${\mu}$m of the proposed device and through a 0.18-${\mu}$m BCD process. Fig. 6 shows the layout of the proposed device designed in the 0.18-${\mu}$m process and the fabrication result, magnified by 50 times. To evaluate the electrical characteristics of the devices, this study used transmission-line-pulse (TLP) measurements with a 10-ns rising time and 100-ns pulse width ^[19]. Fig. 7 shows the TLP I-V curves of the conventional LVTSCR, LTDDSCR and the proposed device. The proposed device was optimized for 12-V class applications; therefore, the ESD design window was formed between 13.2 V, which is a 10\% added margin to the supply voltage (12 V) to protect the IC, and 25 V, which is the oxide breakdown voltage provided in the 0.18-${\mu}$m BCD process ^[20]. The oxide breakdown was evaluated via a 100-ns TLP system. The measurements results imply that LVTSCR is unsuitable for 12-V class IC applications with a low holding voltage of 4.19 V, and operated as a diode with low doping concentration in negative ESD mode with a very low level of current drive capability. In contrast, LTDDSCR exhibited a symmetrical structure and secured bi-directional characteristics; however, it yielded a holding voltage of 6.22 V. Thus, it is also vulnerable to latch-up. Finally, the proposed protection device yielded trigger and holding voltages of 18.75 and 14.24 V, respectively, thus demonstrating its suitability for the 12-V class design window. This is because the SCR loop gain decreased owing to the additional parasitic NPN BJT (Q$_{\mathrm{N4}}$), which resulted from the structural design. Subsequently, it was confirmed that the holding voltage may be increased to above 13.2 V by further optimizing the holding voltage. Moreover, it was confirmed that the anode and cathode exhibited the same discharge path for ESD surges similar to that in LTDDSCR. Table 1 summarizes the electrical characteristics of experimental devices in the forward ESD mode (PAD_A to PAD_B).

Fig. 6. (a) Layout; (b) magnified image of the proposed device fabricated via 0.18-μm process.

Fig. 7. TLP measurement results of LVTSCR, LTDDSCR and the proposed device.

2. Optimization of Electrical Characteristics through Design Variables

Fig. 8(a) shows the design variables L1, L2, and L3 of the proposed device. The electrical characteristics of the proposed device can be optimized through adjustments to the lengths of design variables L1, L2, and L3. The design variable L1 was the interval between the two P-drift regions, and through L1, the N well, which is the base region of the Q$_{\mathrm{P}}$, can be adjusted. The design variable L2 was the area where the P-drift contacted the P-well, and was the point where the effective bases of Q$_{\mathrm{N1}}$ and Q$_{\mathrm{N2}}$ were formed. Finally, the design variable L3 is the part where P-drift was in contact with N-well. With increase in L3, the base areas of Q$_{\mathrm{N1}}$ and Q$_{\mathrm{N2}}$ increased, and the P-drift resistance after avalanche breakdown increased. Consequently, the collector voltage of the additional parasitic bipolar transistors Q$_{\mathrm{N3}}$ and Q$_{\mathrm{N4}}$ also increased simultaneously. Fig. 8(b) shows the layout with segment emitters with 1:1 ratio applied to each terminal. As the emitter area becomes narrower, the emitter injection efficiency of the parasitic bipolar transistor decreases, base recombination increases, and the voltage drop across the device increases. Thus, the segment emitter can increase the holding voltage without increasing the length of the device; thus, it is one of the effective optimization methods for dual directional SCR. In this experiment, the most efficient 1:1 ratio for dual SCR structure segment emitter was applied ^[21,22]. Fig. 8 shows the respective TLP curves obtained when the design variables L1, L2, and L3 were increased.

Design variable L1 in Fig. 9(a) increased by 2 ${\mu}$m, L2 and L3 in Fig. 9(b) and (c) increased by 1 ${\mu}$m to maintain the symmetry of the device. With increase in the design variable L1, the holding voltage of the proposed device increased from 11.31 to 13.09 V over this range. Additionally, the holding voltage increased to 13.63 V with increase in the design variable L2. Whereas, increasing the length of the design variable L3 induced a large increase in holding voltage of 14.24 V. This is because with increase in the design variable L3, the collector voltages of Q$_{\mathrm{N3}}$ and Q$_{\mathrm{N4}}$ as well as base regions of Q$_{\mathrm{N1}}$ and Q$_{\mathrm{N2}}$ increased simultaneously. The drift resistance of the P+ bridge region increases so that a larger voltage is applied to the collectors of Q$_{\mathrm{N3}}$ and Q$_{\mathrm{N4}}$. Further, as the collector voltage increased, more current flowed through Q$_{\mathrm{N3}}$ and Q$_{\mathrm{N4}}$, thus reducing the SCR loop gain. Therefore, the proposed device can effectively perform holding voltage engineering through adjustments to design variable L3.

Considering the relatively long current discharge path of the dual SCR where the well area was further formed, the result of TLP evaluation via the application of the segment emitter to the proposed device is shown in Fig. 10. With increase in the number of segments, for all parasitic bipolar transistors (positive mode: Q$_{\mathrm{N2}}$, Q$_{\mathrm{N4}}$, and Q$_{\mathrm{P}}$, negative mode: Q$_{\mathrm{N1}}$, Q$_{\mathrm{N3,}}$ and Q$_{\mathrm{P}}$), the emitter injection efficiency decreased, resulting in an increase in the voltage drop across the device. In this experiment, the design variables L1, L2, and L3 held the minimum rule of the process. The experimental results indicate that with increase in the number of segments 0 to 11, the holding voltage increased significantly up to 15.71 V as shown in Fig. 10. Increasing the number of segments increases the perimeter of the junction of the anode and cathode. The depletion layer formed at the junction also increases and the emitter injection efficiency decreases, thereby increasing the holding voltage. However, the narrower emitter caused a large drop in the secondary trigger current owing to the field concentration effect. Therefore, engineers can adjust the operating voltage of the proposed device via the application of the segment emitter while considering the reduced secondary trigger current. Table 2 summarizes the electrical characteristics of the proposed device owing to the design parameters and number of segments.

Fig. 8. Top view of the proposed device with (a) design variables; (b) 11 segment.

Fig. 9. TLP I-V characteristic curves of the proposed device according to changes in (a) L1; (b) L2; (c) L3 design variables.

Fig. 10. TLP I-V characteristic curves of the proposed device according to changes in segment number.

3. Transient Latch-up (TLU) Experiments Results

Transient latch-up (TLU) experiments were performed to verify the latch-up resistance of the conventional LVTSCR, LTDDSCR, and the proposed device in 12 V class applications ^[23]. Fig. 11 shows the output waveform according to the TLU experiment of the experimental devices. In this experiment, L1, L2, and L3 of the proposed device were optimized to 1.5, 1.0, and 3.0 ${\mathrm{\mu}}$m, respectively, and the segment emitter was not applied. In this experiment, the power supply provided 12~V DC voltage corresponding to the operating voltage (V$_{\mathrm{op}}$) of the core IC to PAD_A (anode), and PAD_B (cathode) was grounded. In addition, an initial voltage of 24 V charged to 200 pF was applied instantaneously ^[24]. The oscilloscope outputs an output waveform through two channels, voltage and current. The latch-up immunity characteristics of each ESD device were verified through the TLU test, and the latch-up immunity characteristics were highly related to the holding voltage and current. The experimental results in Fig. 10 show that the LVTSCR had a voltage and current hold-up of 9.3 V and 170 mA, respectively, whereas for LTDDSCR they were 6.8 V and 180 mA, respectively. These numbers corresponded to the holding voltage and current of each device and indicate that the device is not completely cut off. In contrast, in the case of the proposed device, as the power supply voltage returned to 12~V after triggering, the latch-up immunity characteristic was confirmed, as shown in Fig. 10(c).

Fig. 11. Transient latch-up experiment results: (a) LVTSCR; (b) LTDDSCR; (d) the proposed device.

4. High-temperature Experiments Results

High-temperature characteristics are required in ESD protection devices because they impact the electrical characteristics of these devices ^[25,26]. Therefore, we performed a thermal reliability experiment using a hot-chuck control system. Fig. 12 shows the thermal reliability experiment results obtained at high temperatures (300 - 500 K). The reduction in mobility observed at high temperatures increased the resistance of the current path. Consequently, the holding current reduced. Therefore, with decrease in the forward bias of the NPN/PNP BJT parasitic bipolar transistor, the holding voltage decreased and heat loss occurred. According to the measurements, the holding voltage of the proposed device was 12.04 V, which is still higher than the operating voltage of the core IC. In addition, a larger margin can be obtained via the optimization of the holding voltage, as preformed in the earlier experiment. At a high temperature of 500 K, a holding current of 0.21 A and an on-resistance of 2.4 ${\Omega}$ were observed, and the secondary trigger current was 4 A. The robustness was still better than that of HBM 4k. Thus, based on these results, the proposed device exhibits excellent thermal reliability.

Fig. 12. Electrical characteristics of the proposed device in high -temperature (300 to 500 K) environment.