1. Proposal of Dipolar Source Structures

Table 2 summarizes the typical process conditions and device dimensions for DDDNMOS standard device. Fig. 2(a) schematically shows the structure of DDDNMOS standard device for high voltage operation ^[17]. The structure has a double diffusion drain surrounding the N$^{+}$ drain region with an N$^{-}$ drift diffusion region, and was designed so that the gate and N$^{+}$ drain regions are not adjacent to each other. The N$^{+}$ drain region was implanted at a high dose of ~10$^{15}$ cm$^{-2}$, and the N$^{-}$ drift region surrounding the drain was implanted at a relatively low dose of ~10$^{13}$ cm$^{-2}$. Additionally, the P-well area forming the channel was implanted with ions lower than the N$^{-}$ drift area in the range of ~10$^{12}$ cm$^{-2}$. Fig. 2(b) shows the dipolar source structure newly proposed in this paper. The dipolar source structure was split under the three conditions as shown in Table 3, expecting that the channel blocking effect by the added P$^{+}$ diffusion would vary depending on the ion implantation dose and the width of the P$^{+}$ diffusion layer.

Fig. 2. Schematic diagrams of DDDNMOS device for high voltage operation: (a) Standard device; (b) Modified device with dipolar source structure proposed in this paper.

It is known that the reason why the DDDNMOS device transitions to the second on-state is that electrons injected from the source form a deep channel under the gate in a high current situation ^[14,15]. Therefore, when forming the source region, as shown in Fig. 2(b), the channel is intentionally blocked by adding a P$^{+}$ diffusion layer next to the existing N$^{+}$ source. If this P$^{+}$ diffusion layer is placed between the existing N$^{+}$ source and N$^{+}$ drain, electron channeling can be prevented from occurring under the gate. That is, since the added P$^{+}$ diffusion layer hinders the flow of electrons injected from the N$^{+}$ source, the electrons do not flow directly down the gate and are evenly distributed in the depth direction of the device. Therefore, since the device does not transition to the second on-state and remains in the first on-state, the double snapback phenomenon can be prevented.

2. Determination of Doping Concentration

As shown in Table 1, MOS transistors operating under ESD stress must satisfy the condition that avalanche breakdown voltage (V$_{\mathrm{av}}$) must be greater than the operation voltage (V$_{\mathrm{op}}$), so the doping concentration of the N$^{-}$ drift/P-well junction region, indicated by the right circle in Fig. 2, plays a very important role ^[5]. Since the avalanche breakdown voltage (V$_{\mathrm{av}}$) is determined by the impurity concentrations of the two regions with opposite polarities, the V$_{\mathrm{av}}$ of the NMOS transistor with the DDD structure is determined by the lateral breakdown voltage of the N$^{-}$ drift/P-well junction. In other words, it can be seen that it is determined by the implantation amount of ions injected into the N$^{-}$ drift region and the P-well region. In general, the lower the impurity concentration of the two regions, the higher V$_{\mathrm{av}}$ tends to be. Therefore, when the DDD structure is applied, since the impurity concentration of the N$^{-}$ drift region in contact with the P-well region can be sufficiently lowered, a high V$_{\mathrm{av}}$ of a desired value can be obtained.

3. Simulation Analysis Method

The structure of the DDDNMOS device was designed using the TMA process simulation tool (@TSUPREM), and the process simulation was performed using the standard high voltage process of 0.18~${\mu}$m_30~V technology. In order to examine the effect of implantation amount of P-well, N$^{-}$drift, and N$^{+}$ drain on the double snapback phenomenon, the optimal implantation range was determined by performing repeated simulations using a 2D matrix combination.

The device structure designed using TSUPREM4 was input as a file to the ISE tool, mesh optimization (@MDRAW) was performed, and device simulation (@DESSIS) was performed. The high-current operating characteristics of the DDDNMOS device were analyzed using a two-dimensional simulation including thermal effects. To simulate the ESD stress of the human body model (HBM), a mixed mode transient (MMT) simulation was performed by applying a trapezoidal current pulse with a rise time of 10 ns and a duration time of 100 ns. A transmission line pulse (TLP) measurement system, Barth 4002, was used to monitor the high-current response of the fabricated DDDNMOS device ^[16]. During the measurement, the rise time and duration of the pulse were maintained at 10 ns and 100 ns, respectively.

1. Influence of Process Parameters

Fig. 3 shows a comparison of measured TLP I-V characteristics according to changes in P-well ion implantation amounts. The double snapback phenomenon occurred regardless of the change in well implantation amount. That is, it can be seen that the amount of P-well implantation does not fundamentally change the conduction mechanism in the high current region. In addition, when the amounts of P-well ion implantation increased, the first on-state in the TLP I-V curve in the high current region was reduced, and the second on-state was expanded. When the amount of well ion implantation increased, V$_{\mathrm{h}}$ and R$_{\mathrm{on}}$ decreased, and I$_{\mathrm{tb}}$ showed a tendency to increase. There was no significant change in the contour distribution of current and electric field density according to the ion implantation change of the P-well region.

Fig. 3. Comparison of measured TLP I-V characteristics according to P-well ion implantation amounts.

Fig. 4 shows the measured TLP I-V characteristics according to the change in N$^{-}$ drift ion implantation amounts. As the N$^{-}$ drift ion implantation amount increased, the leakage current increased and V$_{\mathrm{av}}$ decreased. Here, it can be seen that the amount of N$^{-}$ drift ion implantation is an important factor in determining whether double snapback occurs. That is, if the N$^{-}$ drift ion implantation amount is maintained above a specific threshold value, a deep channel is not formed under the gate even in a high current region, so that a transition from the first on-state to the second on-state is not made, so good ESD protection performance can be obtained.

Fig. 4. Measured TLP I-V characteristics according to N- drift implantation amounts.

In summary, when the N$^{-}$ drift ion implantation amount is less than 1.1${\times}$10$^{13}$ cm$^{-2}$, a double snapback occurs because a deep electron channel is formed under the gate when the total current reaches a threshold value or more. On the other hand, when the N$^{-}$ drift ion implantation amount is more than 3.3${\times}$10$^{13}$ cm$^{-2}$, even if the total current increases, the electron channel is not formed under the gate and double snapback does not occur, so the first on-state is maintained until thermal breakdown occurs.

Fig. 5 compares the measured TLP I-V characteristics according to changes in N$^{+}$source/drain ion implantation amounts. Even when the source/drain ion implantation amount was changed within the range of 5.0${\times}$10$^{14}$ to 5.0${\times}$10$^{16}$ cm$^{-2}$, the measured TLP I-V characteristics of DDDNMOS did not change at all. That is, it can be seen that changing the ion implantation amount for the source/drain region has no effect on the ESD protection performance of the DDDNMOS device.

Fig. 5. Comparison of measured TLP I-V characteristics according to N+source/drain ion implantation amounts.

2. Simulation Characteristics of the Dipolar Source Structure

According to the results of the previous section, it was found that if the N$^{-}$ drift ion implantation amount is properly adjusted among the process parameters, the transition from the first on-state to the second on-state can be prevented under high current conditions and more stable ESD protection performance can be realized. However, if the N$^{-}$ drift ion implantation amount is continuously increased, the avalanche breakdown voltage of the device is lowered, and thus cannot be applied when the operating voltage is greater than 30~V. Therefore, in order to prevent the transition to the second on-state while maintaining the avalanche breakdown voltage of the device, a method of changing the ion implantation amounts or structure on the N$^{+}$ source could be an alternative without changing the ion implantation amounts of P-well, N$^{-}$ drift, and N$^{+}$ drain region.

In order to discuss the improvement of the ESD protection performance of the dipolar source structure proposed in this study, a simulation was performed using mixed-mode transient analysis, which simultaneously performs device and circuit simulation. And, the thermal breakdown phenomenon was analyzed through electron density, current flow, electric field, and maximum temperature distribution inside the device.

Fig. 6 shows the simulated MMT I-V characteristics to consider the change of the electron channel according to the three type of dipolar source (half-, quarter-, and entire-type) structures proposed in this study shown in Table 3. The proposed dipolar source structures exhibited more improved I-V characteristics than the DDDNMOS standard device, and in particular, the entire-type dipolar source structure suppressed the double snapback phenomenon as expected. That is, if the P$^{+}$ diffusion layer is added between the N$^{+}$ source and the N$^{+}$ drain, since the P$^{+}$ diffusion layer hinders the flow of electrons injected from the N$^{+}$source, the formation of electron channeling under the gate can be prevented. Thus, it is believed that the device can be forced to remain in the first on-state until thermal breakdown occurs. As shown in Fig. 6, the double snapback phenomenon appeared in the standard device, quarter- and half-type dipolar source device, but it can be confirmed that the double snapback phenomenon is suppressed in the entire-type dipolar source structure. As a result of the simulation of the DDDNMOS device with the above three structures of dipolar source, it was found that the avalanche breakdown voltage was the same as that of the DDDNMOS of the standard structure, but significantly improved ESD protection performance could be realized. That is, the entire-type of dipolar source structure showed improved characteristics in which the double snapback phenomenon did not appear compared to the quarter- and half-type dipolar source structure.

Fig. 6. Comparison of I-V characteristics of standard devices and modified devices with three-type of dipolar source proposed in this study. (Half-type: current=9.0 mA/um, Entire-type: current=6.0 mA/um).

The channel blocking phenomenon expected in Fig. 6 can be clearly confirmed through the contour analysis results shown in Fig. 7. That is, it can be seen that the electron channel is not formed until the thermal breakdown phenomenon occurs, and the electric field is evenly distributed.

Fig. 7. Contour distribution of each dipolar source structure for electron channels: (a) Standard device, Current=8.0 mA/μm; (b) Half-type structure, Current=9.0 mA/μm; (c) Entire-type structure, Current=6.0 mA/ μm.

That is, the DDNMOS device with dipolar source structure as shown in Fig. 7(b) and (c) will be able to realize significantly improved ESD protection performance compared to the standard device as shown in Fig. 7(a). As described above, it means that electron channeling and occurrence of the second on-state can be surely prevented by adjusting the width and implantation amount of the added P$^{+}$ diffusion layer to a certain threshold value.

Fig. 8 shows the I-V characteristics of a device with the same N$^{-}$ drift ion implantation amount and half-type dipolar source structure as in Fig. 8. The DDDNMOS standard device (○) with an ion implantation amount of 1.1${\times}$10$^{13}$cm$^{-2}$ formed a deep electron channel under the gate by the electron-rich region extending from the source to the drain, as shown in Fig. 8. As a result, a double snapback that transitions from the first on-state to the second on-state occurred. That is, when the DDDNMOS standard device transfers to the second on-state, it exhibits very unstable I-V characteristics, so good ESD protection performance cannot be realized.

Fig. 8. I-V characteristics of standard device and half-type dipolar structure device: (a) DDDNMOS standard device with a drift ion implant amount of 1.1×1013cm-2(○); (b) DDDNMOS standard device with a drift ion implant amount of 3.3×1013cm-2(△); (c) modified DDDNMOS device (■) with half-type dipolar source.

According to previous research results, among various process parameters, the amount of N$^{-}$ drift ion implantation was found to be a critical factor that can control the double snapback phenomenon that occurs in DDDNMOS standard devices. Therefore, in order to improve the unstable ESD protection characteristics of the standard device, as shown in Fig. 8(b) and (c), if the N$^{-}$ drift ion implantation amount is maintained at 3.3${\times}$10$^{13}$~cm$^{-2}$ or more (${\bigtriangleup}$) or modified to the half-type dipolar source (${\blacksquare}$), since the transition from the first on-state to the second on-state can be prevented, stable ESD protection performance can be realized. Since the drift ion implantation amount also affects the leakage current and the avalanche breakdown voltage, the method of maintaining the N$^{-}$ drift ion implantation amount at 3.3${\times}$10$^{13}$~cm$^{-2}$ or more can be applied only to DDDNMOS standard devices with an operating voltage of 30~V or less. Therefore, stable ESD protection performance can be realized by using a modified device having a new structure such as dipolar sources for a process technology in which the operating voltage is higher than 30~V.

Fig. 9 compares the contour distribution of electron density according to the current change in the case of a standard device with different N$^{-}$ drift ion implantation amount and a device with half-type dipolar source. As shown in Fig. 9(a), in the case of a standard device with an N$^{-}$ drift ion implantation amount of 1.1${\times}$10$^{13}$~cm$^{-2}$, the electron-rich region gradually expanded from the source to the drain side as the current density flowing between the drain and the source increased. The electron-rich region initially flows in a vertical direction along the BJT current path, and the device exhibits normal I-V characteristics of the BJT when the U-shaped current path is maintained.

Fig. 9. Current dependences of electron density: (a) Standard device with a drift ion implantation amount of 1.1×1013cm-2; (b) Standard device with a drift implantation amount of 3.3×1013cm-2; (c) DDDNMOS device with half-type dipolar source.

When the N$^{-}$ drift ion implantation amount was 1.1${\times}$10$^{13}$cm$^{-2}$ or less, the electron-rich region expanded toward the side of the device as the current density increased, forming a channel under the gate. When the channel is formed under the gate, a low-resistance current path is formed between the source and drain, so it transitions from the first on-state showing normal I-V characteristics to the second on-state, resulting in low snapback holding voltage and low on-resistance characteristics.

However, as shown in Fig. 9(b), when the N$^{-}$ drift ion implantation amount is 3.3${\times}$10$^{13}$~cm$^{-2}$ or more, even if the current density increases, the electron-rich region does not expand beyond a certain limit in the lateral direction of the device, so no channel is formed under the gate. Therefore, since a U-shaped BJT current path is always formed regardless of the current density, there is an advantage in that the first on-state can be continuously maintained without transition to the second on-state.

In addition, as shown in Fig. 9(c), in the case of the device with half-type dipolar source, when a P$^{+}$ diffusion region was added between the N$^{+}$ source and the N$^{+}$ drain, the P$^{+}$ diffusion hindered the formation of an electron channel, so no channel was formed under the gate. As a result, it can be predicted that the transition to the second on-state is not made and remains in the first on-state.

In the previous section, it was explained that if the N$^{-}$ drift ion implantation amount is optimally designed among the process parameters, it prevents the device from transition from the first on-state to the second on-state in the high current region, realizing very good ESD protection performance. However, if the N$^{-}$ drift ion implantation amount is increased, the double snapback of the device can be prevented, but the problem is that it cannot be applied to an operating voltage higher than 30V because the V$_{\mathrm{av}}$ value is relatively low. Therefore, in order to prevent the transition from the first on-state to the second on-state while maintaining the V$_{\mathrm{av}}$ value at a desired value, an alternative method may be to change the implantation conditions or structure of the source while maintaining the P-well/N$^{-}$ drift/N$^{+}$ drain implantation conditions.

That is, when the P$^{+}$ diffusion layer is formed as a dipolar source between the N$^{+}$ source and the N$^{+}$ drain, the flow of electrons injected from the N$^{+}$ source is hindered, thereby preventing the formation of an electron channel under the gate. Therefore, the first on-state can be further maintained until thermal breakdown occurs. Therefore, as a result of simulation on the device having the various dipolar source structure shown in Table 3, it was found that V$_{\mathrm{av}}$ has improved ESD protection performance that prevents double snapback while being the same as the standard device ^[7]. In addition, it was confirmed from the contour distribution result that the electron channel was not formed until thermal breakdown occurred, and the electric field was dispersed. That is, it was found that the DDDNMOS of the dipolar source structure has the effect of reliably preventing the occurrence of electron channels and second on-state by optimizing the size of the added P$^{+}$ diffusion region and the amounts of ion implantation.