JungHoyong1,2
DoWonkyu1
ParkCheonwi2
KoJaehong2
JangYoung-Chan1,†
-
(Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi,
Gyungbuk, Korea )
-
(DDI Design 1 Team, DB GlobalChip, Seongnam-si, Gyunggi-do, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Pipelined SAR analog-to-digital converter, flash ADC, residue amplifier, conversion pause function
I. INTRODUCTION
Recently, an active matrix organic light-emitting diode (AMOLED) has been widely used
for mobile and television display applications. Because the threshold voltage of AMOLEDs
changes over time due to the aging phenomenon of the pixels, displays using AMOLEDs
require circuits to detect and compensate for the pixel aging. The pixel aging compensation
circuit uses an analog-to-digital converters (ADC) to sense the threshold voltage
of each pixel. In addition, as displays become larger and more highly specified, it
requires ADCs with sampling rates of tens of MHz and resolutions of 10-bit or higher.
To detect pixel aging in large AMOLED displays that are subject to various noises,
a pipeline ADC can be used that uses digital error correction logic to perform reliable
data conversion.
Fig. 1(a) shows a block diagram of a conventional pipelined ADC consisting of four stages to
achieve a resolution of 12 bits. Except for the last stage, each stage uses both a
flash ADC (FADC) and a residue amplifier to perform the multiplication. These blocks
in each stage become the main blocks that increase the overall power consumption of
the pipelined ADC [1-3]. To reduce the power consumption, the pipelined ADC shown in Fig. 1(b) used a successive approximation register (SAR) ADC instead of a FADC. The SAR ADC
can reduce the power consumption by using only one comparator and a capacitor digital-to-analog
converter (CDAC) instead of a resistor DAC. However, the SAR ADC requires multiple
clock cycles for a single data conversion, and the residue voltage of each stage,
which is determined by the output value of the CDAC after the data conversion of the
SAR ADC, may have a lost due to the charge sharing by the parasitic capacitors of
the CDAC [4-6]. Fig. 1(c) shows a design technique that shares the FADC and residue amplifiers used in the
two stages of the pipelined ADC [7-9]. Main static current consumption of pipelined ADC can be reduced. This structure
can reduce power consumption compared to the conventional structure in Fig. 1(a), but it still has limitations in reducing power consumption due to the use of FADCs
and residue amplifiers for stages 3 and 4.
Fig. 1. Architecture of pipelined ADCs: (a) conventional architecture; (b) pipelined SAR architecture; (c) architecture sharing of FADC and residue amplifier.
A 12-bit 10-MS/s pipelined SAR ADC consisting three stages is proposed in this paper.
It uses a sharing scheme for the FADC and residue amplifier for stages 1 and 2, and
a SAR ADC for the final stage that is free from the issue of residue voltage. The
SAR ADC used in the last stage has an asynchronous structure to eliminate additional
clock cycles. Additionally, it has a conversion pause function to stabilize the reference
voltage through non-overlapping operation between the FADC and SAR ADC and thereby
improve the performance of the pipelined SAR ADC.
Section II explains the operation, including block and timing diagrams of the proposed
pipelined SAR ADC. In addition, design techniques to minimize the area of the pipeline
SAR ADC and the SAR ADC with conversion pause function for stabilization of reference
voltage are described. Section III presents the implementation and simulation results
of the pipelined SAR ADC. Finally, Section IV provides the conclusions of this paper.
II. DESIGN OF 12-BIT 10-MS/S PIPELINED SAR ADC
1. Architecture and Operation of Pipelined SAR ADC
Fig. 2 shows the block and timing diagrams of the proposed pipelined SAR ADC. The Pipeline
SAR ADC consists of three stages and a digital error correction logic (DCL), as shown
in Fig. 2(a). Both the stages 1 and 2 consist of a FADC and multiplying DAC (MDAC). The FADC1
and FADC2 output 3 and 4 bits of digital code, respectively, which actually 2.5 and
3.5 bits of information to apply the digital error correction used in conventional
pipelined ADCs [10,11]. Thus, the MDAC1 and MDAC2 amplify the residue voltage by a factor of 4 and 8, respectively.
The last stage is designed by using a 7-bit asynchronous SAR ADC. The stages 1 and
2 share resistor and comparator arrays for the FADC and a residue amplifier for the
MDAC.
The sharing scheme of the FADC and residue amplifier requires an additional time,
as shown in Fig. 2(b). Therefore, the frequency of external clock (EXCLK) for the proposed pipelined SAR
ADC is set to 20 MHz for a sampling rate of 10 MHz. The non-overlapping clocks Q1
and Q2 are generated by dividing the EXCLK. When the Q1 is high, the analog input
is sampled in the MDAC1 and FADC1 for the operation of the stage 1. The FADC1 samples
the reference voltages for the first active half of the Q1 and converts the analog
input to a 3-bit digital code at the second active half of the Q1. When the Q2 is
high, the residue amplifier performs the amplification operation for the MDAC1: the
first active half of the Q2 is an auto-zero period of the MDAC1, and the residue voltage
is amplified according to the result of the FADC1 during the second active half of
the Q2. While performing the above operation, the amplified residue voltage is sampled
in the MDAC2 of the stage2. Furthermore, the FADC2 converts the amplified residue
voltage to a 4-bit digital output by the same operation as FADC1.
Fig. 2. Proposed pipelined SAR ADC: (a) block diagram; (b) timing diagram.
When the Q1 becomes high again, the MDAC2 performs the auto-zero and amplification
operations according to the result of the FADC2, 4-bit digital code. The amplified
residue voltage is supplied to the stage 3 and sampled in the CDAC of the 7-bit asynchronous
SAR ADC. During this time, the stage 1 samples the new analog input signal using the
MDAC1 and converts the sampled analog input to a digital code. The 7-bit asynchronous
SAR ADC of the stage 3 converts the residue voltage sampled in the CDAC to a digital
code of 7 bits when the Q2 is high again. Finally, the 12-bit digital code, which
is the output of the pipelined SAR ADC, is output through the operation of the DCL
for the digital codes generated in each stage.
2. Sharing of Residue Amplifier for MDAC1 and MDAC2
Fig. 3 shows the block diagram and timing diagram of the MDAC1 and MDAC2 for the stages
1 and 2. The MDAC1 and MDAC2 use four CU1s and eight CU2s to amplify the residue voltage by a factor of four and eight, respectively, as shown
in Fig. 3(a). Additionally, an auto-zeroing capacitor, CA, is added to remove an offset voltage of the residue amplifier. The auto-zeroing
scheme requires additional time for each MDAC. This reduces the time for the residue
amplifier to perform its amplification operation, requiring an increase in the bandwidth
of the residue amplifier. Fig. 3(b) shows the operation time diagram of the MDACs for sharing the residue amplifier.
When the SAMPLE1 signal is high, the analog input is sampled by the DAC of the MDAC1
and FADC1. The MDAC2 and the residue amplifier perform auto-zeroing by the AUTO_ZERO
signal, and the AMP2 amplifies the residue voltage generated by using the digital
output of the FADC2 and feeds it to the 7-bit SAR ADC. When the SAMPLE2 signal is
high, the MDAC1 and the residue amplifier perform auto-zeroing and then amplify the
residue voltage determined by the digital output of the FADC1. The amplified voltage
is then sampled by the DAC of the MDAC2 and FADC2.
Fig. 3. Proposed MDAC: (a) block diagram; (b) timing diagram.
Fig. 4 shows the overall dynamic performance of the pipelined SAR ADC as a function of the
offset voltage of the residue amplifier. When the residue amplifier has an offset
voltage of 5 mV, the effective number of bits (ENOB) decreases by about 2.5 bits.
The auto-zeroing scheme eliminates the offset effect of the residue amplifier, so
that the overall dynamic characteristics of the pipelined SAR ADC are compensated.
Fig. 4. Dynamic performance of ADC according to offset voltage of residue amplifier.
3. Residue Amplifier
The residue amplifiers in stages 1 and 2 must have a voltage gain that can support
the resolution of the residue after their stage, which is 10 and 7 bits, respectively,
accounting for the digital error correction. Therefore, the minimum voltage gains
required for the residue amplifiers of the MDAC1 and MDAC2 are approximately 62 dB
and 44 dB by Eq. (1).
Fig. 5 shows a two-stage operational amplifier circuit for the residue amplifier [12,13]. It consists of two stages: a folded cascode amplifier and a differential amplifier.
Between the output of the first-stage amplifier and the output of the second-stage
amplifier, a capacitor and resistor are added for frequency compensation. In addition,
the CMFB1 and CMFB2 signals are used to maintain the common mode of the output signals
at a constant value and are generated through a common-mode feedback (CMFB) circuit
that utilizes the structure of a switched capacitor for low-power design [14,15]. In this work, one residue amplifier, shown in Fig. 5, is shared for the MDAC1 and MDAC2.
Fig. 5. Circuit diagram of residue amplifier.
Fig. 6(a) shows the frequency response of the designed residue amplifier. The residue amplifier
has a voltage gain of about 116 dB, which is sufficient to meet the voltage gain requirements
for the MDAC1 and MDAC2. The capacitor and resistor added for frequency compensation
between the outputs of the first and second stage amplifiers improve the phase margin
of the residue amplifier from -21$^{\circ}$ to 51$^{\circ}$. The closed-loop voltage
gains of the residue amplifiers in the MDAC1 and MDAC2 are ideally 4 and 8, respectively.
The variations of the closed-loop voltage gains with the magnitude of the output voltage
of the residue amplifier in the two MDACs were simulated to be within 0.113% and 0.125%,
respectively, as shown in Fig. 6(b). The closed-loop voltage gain of the residue amplifier is caused not only by the
variation in the magnitude of the output voltage, but also by the mismatch between
the capacitors used in the MDACs. This closed-loop voltage gain error in the residue
amplifier degrades the overall performance of the pipelined SAR ADC. When the residue
amplifier has a closed-loop voltage gain error of 0.5%, the SNDR of the pipeline SAR
ADC decreases by more than 6 dB. However, this performance degradation is mitigated
by the DCL used in the pipeline SAR ADC, as shown in Fig. 7.
Fig. 6. Simulation results of residue amplifier: (a) frequency response; (b) closed-loop voltage gain.
Fig. 7. Dynamic performance of pipelined SAR ADC according to closed-loop voltage gain error of residue amplifier.
4. Sharing of FADC1 and FADC2
Fig. 8 shows the block and timing diagrams of the FADC for data conversion in the two stages
to reduce the area and power consumption. Fourteen comparators and one resistor string
are used to share the 3-bit FADC1 in stage 1 and the 4-bit FADC2 in stage 2. For the
operation of the stage 1, the IN1 signal is activated and the differential analog
input signals, VINP and VINM, are fed to the FADC. In this case, 6 of the 14 comparators are operational and output
the digital signal of D1<2:0>. For the operation of the 4-bit FADC2 in stage 2, the
IN2 signal is enabled, which causes all 14 comparators to operate and output D2<3:0>.
Meanwhile, the sampling of the reference voltage from the resistor string is done
by the REF signal, which is done every cycle for the operation of FADC1 and FADC2.
On the other hand, like the closed-loop voltage gain error of the residue amplifier
in the MDAC, the offset voltage of the comparators used in the FADC also degrades
the performance of the pipelined SAR ADC, which can also be compensated by the DCL.
Fig. 8. Proposed FADC: (a) block diagram; (b) timing diagram.
5. 7-bit SAR ADC
To reduce power and area, the final stage of the proposed pipelined ADC is designed
as SAR ADC. The proposed SAR ADC shown in Fig. 9(a) consists of a 6-bit CDAC, a comparator, and an asynchronous SAR logic that can perform
a conversion pause function. It samples the output signals of the MDAC2 (VMDACM2, VMDACM2) during the phase Q2 and converts the sampled analog signal into the digital code
D3<6:0> by the asynchronous SAR operation during Q1, as shown in Fig. 9(b) [16,17]. At the end of the sample process, the CLKC signal is enabled and the comparator
performs the comparison operation. When the comparator completes the comparison operation,
it generates the VALID signal, and the generated VALID signal reactivates the CLKC
signal to perform a new comparison operation. In this way, seven comparison operations
are performed asynchronously without an external synchronization signal.
Fig. 9. Proposed SAR ADC: (a) block diagram; (b) timing diagram.
According to the timing diagram of the SAR ADC, the reference sampling of the FADC2
and the asynchronous conversion of the SAR ADC are performed simultaneously. In this
case, the fluctuation of the reference voltage caused by the charge sharing of the
CDAC during the operation of the SAR ADC can introduce noise into the reference sampling
of the FADC2. This reference noise can worsen the overall dynamic characteristics
of the pipelined SAR ADC. The proposed SAR ADC has a conversion pause function to
stabilize the reference voltage through non-overlapping operation between the FADC2
and SAR ADC.
Fig. 10 shows the implementation and operation of the proposed conversion pause function
in the asynchronous SAR logic. To implement the asynchronous SAR conversion, the CLKC
signal is basically generated from the SAMPLE and VALID signals, as shown in Fig. 9(a). The CONV_PAUSE signal shown in Fig. 9(b) is active during the operational portion of FADC2 from the end of sampling the reference
to the beginning of conversion. The activated CONV_PAUSE signal stops the activation
of the CLKC and the conversion of the SAR ADC by holding the VALID signal high. In
this work, the CONV_PAUSE signal is controlled by a binary 2-bit code to have an activation
time of 1.1 ns to 2.1 ns in the simulation case of typical process, voltage, and temperature.
This conversion pause function of the SAR ADC stabilizes the reference voltage by
non-overlapping operation between the FADC and SAR ADC, which can improve the performance
of the pipelined SAR ADC.
Fig. 10. Proposed conversion pause function in asynchronous SAR logic: (a) block diagram; (b) timing diagram.
Fig. 11 shows the dynamic performance results of the pipelined SAR ADC with reference voltage
noise. The reference noise error rate, shown on the x-axis in the Fig. 11, represents the ratio between the voltage magnitude of the reference voltage and
the amplitude of the voltage fluctuation due to switching in the CDAC of the SAR ADC.
As the noise in the reference voltage increases, the dynamic performance of the pipelined
SAR ADC degrades. When the conversion pause function of the proposed SAR ADC is applied,
the dynamic characteristics of the pipelined SAR ADC are improved. Specifically, the
SNDR improves by about 3 dB when noise of magnitude equal to 4% of the reference voltage
is introduced.
Fig. 11. Dynamic performance of pipelined SAR ADC according to reference voltage noise.
III. CHIP IMPLEMENTATION AND SIMULATION RESULTS
The proposed pipelined SAR ADC was designed by using a 180-nm 1-poly 6-metal CMOS
process with a supply voltage of 1.8 V. Its active area is 670 ${\mu}$m ${\times}$
478~${\mu}$m, as shown in Fig. 12. To reduce active area and power consumption, the pipelined SAR ADC used a sharing
scheme for the FADC and residue amplifier for the stages 1 and 2, while the SAR ADC
was used for stage 3. When the frequency of the external clock supplied to the pipelined
SAR ADC is 20 MHz for a sampling rate of 10 MHz, the power consumption of the pipelined
SAR ADC with a differential input voltage range of 2 Vpp is approximately 7.9 mW.
Table 1 shows the power consumption and area of the pipelined SAR ADC designed according
to the sharing scheme for the FADC and residue amplifier for the stages 1 and 2. The
power consumption and area of the pipelined ADC are reduced by 51% and 9%, respectively.
Fig. 13 show the simulated static performances of the 12-bit pipelined SAR ADC. The differential
nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/${-}$0.5 LSBs and +0.43/${-}$0.43
LSBs, respectively, and both values are within +/${-}$0.5 LSBs. Fig. 14 shows the simulated dynamic performances of the pipelined SAR ADC through the fast
fourier transform (FFT). The signal-to-noise and distortion ratio (SNDR) and ENOB
are 73.09 dB and 11.85 bits, respectively, when the 12-bit pipelined SAR ADC operates
at a sampling rate of 10~MHz for a differential analog input signal with low frequency
of 551 kHz. In addition, when the analog input signal is Nyquist frequency of 4.7
MHz, the SNDR and ENOB are 72.97 dB and 11.83 bits, respectively. Table 2 shows the performance comparison of pipelined SAR ADCs. The proposed pipelined SAR
ADC has an ENOB of 11.83 bits and area of 0.282 mm2.
Fig. 12. Layout of designed pipelined SAR ADC.
Fig. 13. Simulated static performances of Pipelined SAR ADC: (a) DNL; (b) INL.
Fig. 14. Simulated dynamic performances of pipelined SAR ADC: (a) low frequency; (b) Nyquist frequency.
Table 1. Power consumption and area of pipelined SAR ADC according to sharing of residue amplifier and FADCs
Table 2. Performance comparison of Pipelined SAR ADCs
IV. CONCLUSIONS
The proposed pipelined SAR ADC with conversion pause function was designed by using
a 180-nm CMOS process with a supply voltage of 1.8 V. The sharing scheme for the FADC
and residue amplifier and the SAR ADC for final stage were used to reduce the active
area and power consumption. Furthermore, the conversion pause function of the SAR
ADC was proposed to improve the reference voltage noise by performing non-overlapping
operations of the FADC2 and SAR ADC. The proposed pipelined SAR ADC had a SNDR of
72.97~dB and an ENOB of 11.83 bits for an analog input signal with a differential
input voltage range of 2 Vpp and with a frequency of 4.7 MHz and a sampling rate of
10 MHz. Its area and power consumption were 0.282~mm2 and 7.9~mW, respectively.
ACKNOWLEDGMENTS
This work was supported by Basic Science Research Program (2020R1I1A3071634) and Priority
Research Centers Program (2018R1A6A1A03024003) through the NRF funded by the Ministry
of Education, and Innovative Human Resource Development for Local Intellectualization
Program (IITP-2024-2020-0-01612) through the IITP funded by the MSIT, Korea. The EDA
tool was supported by the IC Design Education Center, Korea.
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Hoyong Jung was born in Busan, South Korea, in 1994. He received the B.S. and M.S.
degrees from the Department of Electronic Engi-neering, Kumoh National Institute of
Technology, Gumi, South Korea, in 2019 and 2021, respectively. He has been pursuing
a Ph.D. degree since 2021 and joined DB Global Chip, Seongnam, Korea, in 2023. His
current research interests include analog mixed-signal circuit design including data
converters.
Wonkyu Do received the B.S. degree in the department of electronic engineering from
Kumoh National Institute of Technology, Gumi, Korea, in 2021. and the M.S. degree
in electronic engineering from Kumoh National Institute of Technology, Gumi, Korea,
in 2023, respectively. From 2023, he is an engineer in the Core IP group, ABOV semiconductor,
Seoul, Korea, working on analog IP design. His current research interests include
the design of data converters.
Cheonwi Park received the B.S. degree in electronic engineering from Inha University,
Incheon, Korea, in 2009. He received the M.S. and Ph.D. degrees in school of electrical
engineering and computer science from Gwangju Institute of Science and Technology
(GIST), Gwangju, Korea, in 2011 and 2020, respectively. Since 2020, he has been a
senior design engineer at DB GlobalChip, Seongnam-si, Korea, where he has been involved
in the development of various display driver ICs. His research interests include high-resolution
analog to digital converters, readout ICs including analog front ends, and high-slew-rate,
low-offset amplifiers.
Jaehong Ko received the B.S., M.S., Ph.D. degrees in the department of electronic
engineering from Korea University, Seoul, Korea, in 2003, 2005, and 2016, respectively.
From 2005 to 2010, he was a senior engineer in Samsung Electronics, Korea. From 2010
to 2015, he was a Senior Engineer in the Magnachip Semiconductor, Korea. In 2015,
he joined at DB GlobalChip, Seongnam-si, Korea, where he is a vice president design
1 team leader and is involved in the development of various display driver ICs.
Young-Chan Jang received the B.S. degree in the department of electronic engineering
from Kyungpook National University, Daegu, Korea, in 1999 and the M.S. and Ph.D. degrees
in electronic engineering from Pohang University of Science and Technology (POSTECH),
Pohang, Korea, in 2001 and 2005, respectively. From 2005 to 2009, he was a Senior
Engineer in the Memory Division, Samsung Electronics, Hwasung, Korea, working on high-speed
interface circuit design and next-generation DRAM. In 2009, he joined the School of
Electronic Engineering, Kumoh National Institute of Technology, Gumi, Korea, as a
Faculty Member, where he is currently Professor. His current research area is high-performance
mixed-mode circuit design for VLSI systems such as high-performance signaling, clock
generation, and analog-to-digital conversion.