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Title A 12-bit 10-MS/s Pipelined SAR ADC Sharing Flash ADC and Residue Amplifier of Multiplying DAC
Authors (Hoyong Jung);(Wonkyu Do);(Cheonwi Park);(Jaehong Ko);(Young-Chan Jang)
Page pp.128-137
ISSN 1598-1657
Keywords Pipelined SAR analog-to-digital converter; flash ADC; residue amplifier; conversion pause function
Abstract A pipelined successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for display applications. It consists of three stages and a digital error correction logic (DCL). To reduce the power consumption and area of the proposed pipelined SAR ADC, the flash ADC (FADC) and the residue amplifier of the stages 1 and 2 are shared, and the stage 3 has an architecture of 7-bit asynchronous SAR ADC using a capacitor digital-to-analog converter (CDAC). The conversion pause function of the 7-bit asynchronous SAR ADC improves the performance of the pipelined SAR ADC by stabilizing the reference voltages through non-overlapping operation between the FADC and SAR ADC. The proposed pipelined SAR ADC is designed using a 180-nm CMOS process with a supply of 1.8V. The designed pipelined SAR ADC has a SNDR of 72.97 dB and an ENOB of 11.83 bits for an analog input signal with a frequency of 4.7 MHz at a sampling rate of 10 MHz. Its area and power consumption are 0.282 mm2 and 7.9 mW, respectively.