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  1. (Department of Electrical and Electronics Engineering, Kangwon National University, Chuncheon-si, Gangwon-do, Korea)

Bayesian optimization, phase-locked loop, phase noise, integrated phase noise (IPN), delta-sigma modulator


In the existing RF phase lock loop (PLL) and circuit measurement, the conventional approach involves manually finding the optimal value one by one. However, this method has several drawbacks. First, it is a time-consuming process that can significantly delay the experimentation phase. Second, it often leads to inaccurate data recording due to human errors or inconsistencies. Finally, relying on human judgment to identify the optimal value introduces the possibility of errors and subjectivity.

To address these issues, we propose a machine learning method for the measurement and test automation in the PLL circuit [1]. By automating the measurement process, human errors can be minimized, and consistent and reliable data can be obtained for each experiment. This automation approach allows for a more efficient and effective evaluation of RF PLL and circuit performance. Furthermore, this paper specifically focuses on reducing the number of experiments required. As the number of measurement parameters used for optimizaton increases, the traditional approach necessitates an exponential increase in the number of measurements.

To acheive this goal, we employ Bayesian optimization (BO) algorithm. The BO algorithm intelligently explores the parameter space, efficiently narrowing down the search to the most promising regions. As a result, the sub-optimal values of the variables can be identified more quickly and accurately. Overall, we present a methodology that combines measurement automation and BO to enhance the efficiency and accuracy of RF PLL and circuit measurements. By adopting this approach, circuit designers can significantly reduce the time and effort required for experimentation while obtaining reliable results.


1. PLL Structure

Fig. 1 illustrates the block diagram of the RF PLL system, which consists of several key blocks. The main blocks include the phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage controlled oscillator (VCO), and multi-modulus divider (MMD). These blocks work together to ensure the proper functioning of the PLL [2,3].

Fig. 1. RF PLL structure used for measurement.

The PFD compares the external reference (REF) signal with the DIV which is the VCO output divided by N.Frac. It then generates UP and DN signals, which correspond to positive and negative frequency phase differences, respectively.

The UP and DN signals are then fed into the charge pump circuit (CPC), which converts them into the corresponding currents. The CPC adjusts the input voltage of the VCO based on the voltage from the LF. Then, the VCO generates a voltage-controlled oscillating signal. The MMD component divides the VCO output signal by a division ratio specified by N.Frac. This division is necessary to produce the desired output frequency.

Fig. 2 illustrates the structure of CPC. In this figure, we see that CPC consists of 63 UP current sources (UCS) and 63 DN current sources (DCS). Each of them has charge pump circuit bias (CPCB) value which determines its current amount. Thus, we can generate the current amounts of the UCS and the DCS by combinations of the switch positions and the CPCB.

Fig. 2. CPC structure used for measurement.

In this paper, we focus on finding the optimal integrated phase noise (IPN) value of the PLL. The control variables that significantly impact the performance of the CPC are charge pump circuit whole bias (CPCB), UP current (VBP), and DN current (VBN). CPCB adjusts the bias current of the bandgap circuit that supplies the CPC, while VBP and VBN control the ratio of PMOS and NMOS currents in the CPC [2].

In such a fractional-N PLL, the out-band quantization noise of delta-sigma modulation (DSM) is folded into the in-band region due to nonlinearity of PFD-CP circuits. A simple and effective way to block the effect of noise folding is to move the lock point to a more linear region on the transfer function. So, we measured the optimal IPN by adjusting the CP offset current [4].

The IPN is an integrated measure of phase noise and is commonly used to assess the performance of a PLL. Phase noise (PN) is a frequency domain measurement that quantifies the undesirable fluctuations or noise in the phase of a signal. It is crucial for the PN to have a low value as it can adversely affect signal modulation.

3. IPN Data Acquisition

The IPN data of the RF PLL was obtained using automated measurement techniques. The measurement automation setup is illustrated in Fig. 3. A DC power supply provides a constant voltage to the motherboard, which in turn supplies a constant voltage to both the device under test (DUT) board and the serial peripheral interface (SPI) module.

Fig. 3. Proposed automatic measurement structure for PLL.

By establishing SPI communication between the personal computer (PC) and the SPI module, the dominant variables of the RF PLL on the DUT board can be controlled. Once the desired parameters are set, the IPN of the RF PLL is measured using a Phase Noise Analyzer. To facilitate the measurement process, the general-purpose interface bus (GPIB) is employed. The IPN data obtained through the Phase Noise Analyzer is then saved in comma-separated values (CSV) format using the PC as a storage medium.

4. Exhaustive Search

Exhaustive search (ES), also known as brute-force search, is a simple and straightforward algorithmic technique used to solve problems by systematically checking all possible solutions. It involves considering every possible candidate solution and evaluating each one to determine if it meets the problem requirements.

The ES method was initially employed to obtain the IPN values for three different RF PLL chips. The search method involved sequentially varying each control variable, namely CPCB, VBP, and VBN, and recording the resulting performance values. Since each control variable could have an N-bit variation, the total number of measurements required would be $2^{3N}$ to cover all possible IPN values. However, considering the need to reduce measurement time, we imposed an limitation of only allowing 20 points of variables for each control variable. Consequently, a total of 8000 measurements were performed, covering a subset of IPN values, to identify the most optimal IPN value among them.

Fig. 4-6 illustrate the IPN values obtained by varying the three control variables for the A3, A5, and A15 boards, respectively. As anticipated, the figures demonstrated that the optimal combination of control variables exists for each circuit. Nonetheless, utilizing the ES to determine the optimal combination of the control variables would be extremely time-consuming.

Fig. 4. IPN characteristics of A3 board.
Fig. 5. IPN characteristics of A5 board.
Fig. 6. IPN characteristics of A15 board.

To address this challenge, we introduce the application of the BO, which enables the identification of sub-optimal control variable combinations with only a small number of measurements. By leveraging BO, the search process becomes more efficient, allowing for a quicker identification of promising regions in the control variable combination space. Consequently, we achieve a significant reduction in the overall measurement time while still obtaining satisfactory results.

5. Bayesian Optimization

In the previous section, the ES method was utilized to perform a comprehensive analysis of IPN values for different control variable combinations. However, due to the time-intensive nature of the ES, we need to consider the optimization method to achieve faster and more efficient measurements, focusing on identifying sub-optimal control variable combinations with a reduced number of experiments.

In the vast landscape of global optimization, BO and genetic algorithms (GA) are two techniques that often take center stage. Each boasts its unique strengths and operational characteristics, making them suitable for diverse challenges. BO, using its probabilistic model-based approach, excels in efficiently finding the maximum of intricate functions with minimal evaluations [5]. In contrast, GA operates on a generational paradigm, often requiring multiple evaluations for each generation [6]. This becomes particularly challenging when optimizing parameters like IPN, where each evaluation bears substantial time and cost implications. In such contexts, the frequent evaluations of GA can escalate expenses quickly. Meanwhile, BO, with its capacity to leverage prior data, ensures fewer, more strategic evaluations. Especially when the cost of evaluations is a crucial factor, BO often stands out as a more economical option over GA.

Specifically, BO aims to solve


where an objective function ../../Resources/ieie/JSTS.2024.24.2.69/image10.png is an expensive-to-evaluate function and ../../Resources/ieie/JSTS.2024.24.2.69/image11.png is a feasible set [5, 7, 8]. If the problem we aim to solve in this paper is interpreted from the perspective of BO, the notations ../../Resources/ieie/JSTS.2024.24.2.69/image12.png, ../../Resources/ieie/JSTS.2024.24.2.69/image13.png, and ../../Resources/ieie/JSTS.2024.24.2.69/image10.png in (1) can be seen as a 3-dimenstional vector representing the combination of control variables, a set comprising all possible 8000 combinations of these control variables, and a function that produces the IPN value multiplied by ‘ ../../Resources/ieie/JSTS.2024.24.2.69/image14.png’ for a given combination of control variables, respectively. The reason for employing this type of objective function is because BO aims to discover a solution that maximizes the objective function.

Because the objective function is not an analytical function, the key idea of BO is to build a probabilistic surrogate model of the objective function using N observations as


which is then used to select the next candidate point of ../../Resources/ieie/JSTS.2024.24.2.69/image16.png by balancing exploration and exploitation. This balance is often achieved via an acquisition function. Furthermore, this process is repeated until either a specified number of iterations has been reached, or the difference between the objective function value of the newly chosen candidate point and that of the preceding point falls below a predetermined threshold. Fig. 7 illustrates the flow chart of BO process.

Fig. 7. Flow chart of Bayesian optimization.

Because the IPN measurement requires a relatively long time, we expect that a suboptimal solution can be found with a small number of measurements through the BO.


The experimental equipment consists of PNA(Phase Noise Analyst), DC supply, and PC. DC supply applies the power of the board and the PC adjusts the variables of the chip. The output of the PLL is measured at the PNA. Data values for performance are stored on the PC and they are used as a black box in the optimization algorithm. Fig. 8 shows environment for measuring IPN of RF PLL.

Fig. 8. RF PLL IPN measurement environment.

To fairly compare BO and GA, one must consider the inherent differences in their operations. BO typically evaluates the objective function at one point per iteration, ensuring a distinct candidate evaluation every time. On the other hand, GA operates based on populations of candidates. During the operation, GA might sometimes re-evaluate the same candidates due to crossover, mutation, or selection operations, leading to potential repeated evaluations [6].

To capture the true essence of the comparison, we compared them based on the number of distinct candidate evaluations. Specifically, we employed a scenario within the GA framework: suppose from a population of 10 candidates, 5 new candidates are generated through the standard genetic operations. If 2 out of these 5 have been previously evaluated in past iterations, they won’t be counted again. Effectively, only the 3 genuinely new candidates will increment our distinct evaluations counter. This approach provides a balanced metric that accounts for the unique way each method searches the solution space. By focusing on the number of unique evaluations (i.e., the number of distinct candidates), we can ensure that both algorithms have the same opportunities to refine their solutions, making the comparison both fair and informative.

With this respect, Fig. 9(a)-(c) show the IPN performance losses of A3, A5, and A15 boards, respectively, due to the BO and the GA compared to the optimal value from the ES. In these figures, the solid line and the dotted line represent the mean loss and the empirical 95th percentile loss, respectively. Also, Table 1 summarizes the performance losses of BO and GA compared to the optimal value at 100 distinct candidates. From these results, we see that the BO universally improved performance of the 95th percentile loss compared to the GA and converges to the near-optimal value with a few iterations.

Table 1. BO and GA loss (dB) at 100 distinct candidates


Opt. Method


95th Perc.






















Fig. 9. Mean and empirical 95th percentile losses of the boards (The solid line and the dotted line represent the mean loss and the empirical 95th percentile loss, respectively).

Fig. 10 shows the measurement results of A3 Board using BO. The blue and the yellow lines represent the IPNs using the solutions at the 1st iteration (i.e., randomly chosen solution) and the 100th iteration, respectively. From this figure, we see that BO noticeably improves the IPN performance.

Fig. 10. A3 Board measurement results using BO (The blue and the yellow lines represent the 1st iteration and the 100th iteration, respectively).


In this paper, we demonstarted that BO can achieves an IPN performance within around 3 dB of the optimal at the 95th percentile while reducing the search time for optimal parameters by 98.75% compared to the ES. Compared to GA, BO universally shows better performance of the 95th percentile loss and converges to the near-optimal value with a few iterations. Therefore, BO using probabilistic model-based approaches is more suitable for optimizing the circuit through measurement. Utilizing this method allows researchers to decrease the amount of time and resources devoted to experimentation, yet still find reliable control variables for the RF PLL.


This study was supported by a research grant of Kangwon National University in 2022, Ministry of Trade, Industry &Energy (MOTIE, Korea) under Industrial Technology Innovation Program (No. 20026426), the Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (P0017011 and P0020966, HRD Program for Industrial Innovation), and the National Research Foundation Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2023-00221494), and project BK21FOUR. The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), Korea.


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Ji-Sub Yoon

Ji-Sub Yoon was born in Seoul in 1998. He graduated from Kangwon National University in 2023 with a B.S degree in electrical engineering. He is currently pursuing his master's degree. His interests are in PLL and digital circuits.

Dong-In Choi

Dong-In Choi was born in Paju in 1998. He graduated from Kangwon National University in 2023 with a B.S degree in electrical engineering. He is currently pursuing his master's degree. His interests are in DC-DC and digital circuits.

Seungyoung Park

Seungyoung Park received the B.E., M.E., and Ph.D. degrees in electrical engineering from Korea University, Seoul, Korea, in 1997, 1999, and 2002, respectively. From April 2003 to December 2005, he was with Samsung Advanced Institute of Technology, Kiheung, Korea, where he was a Senior Engineer, working on several projects in the field of next-generation wireless mobile communications. From January 2006 to February 2007, he was with the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA, where he was a Postdoctoral Research Associate. Since March 2007, he has been with the Department of Electrical and Electronics Engineering, Kangwon National University, Chuncheon, Korea, where he is currently a Professor. Additionally, as of March 2023, he took on the role of research advisor at an autonomous vehicle security technology firm AUTOCRYPT, Co., Ltd., Seoul, Korea. His research interests include machine learning applications in wireless communications, RF circuit, and cyber security.

In-Chul Hwang

In-Chul Hwang received the B.S., M.S., and Ph.D. degrees from Korea University, Seoul, Korea, in 1993, 1995, and 2000, respectively. He was a Research Staff with the Coordinated Science Laboratory, University of Illinois at Urbana Champaign, Champaign, IL, USA, from 2000 to 2001. From 2001 to 2007, he was a Senior Engineer with Samsung Electronics, Kiheung, Korea, where he was involved with CMOS RFIC development targeting for GSM/EDGE/WCDMA RF transceivers. In 2007, he joined the faculty of the Department of Electrical and Electronics Engineering, Kangwon National University, Chuncheon, Korea, where he is currently a Professor. His current research interests include CMOS RFIC, advanced PLLs, and power- and frequency-management ICs.