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Title Performance Optimization of IPN in RF PLL using Bayesian Optimization
Authors (Ji-Sub Yoon);(Doing-In Choi);(Seungyoung Park);(In-Chul Hwang)
DOI https://doi.org/10.5573/JSTS.2024.24.2.69
Page pp.69-75
ISSN 1598-1657
Keywords Bayesian optimization; phase-locked loop; phase noise; integrated phase noise (IPN); delta-sigma modulator
Abstract The performance optimization of a circuit in a short time is one of the important issues for IC testing. Traditional methods depend on domain knowledge and exhaustive search (ES) for feasible parameters. In this paper, we proposed the sub-optimal control of the integrated phase noise (IPN) characteristics of RF phase lock loop (PLL) using a Bayesian optimization. For data acquisition, we designed an autonomous measurement platform based on general purpose interface bus (GPIB) and Python. Using our algorithm, we achieved performance within around 3 dB of the optimal at the 95th percentile and reduced the search time for optimal parameters by at least 98.75% compared to the ES method.