This paper proposes a three-dimensional solenoidal inductor using a “multi-radius multi-path” (MRMP) structure that targets integrated voltage regulators (IVRs). Multi-radius (MR) refers to the inclusion of additional turns inside the solenoid, and multi-path (MP) describes the division of a single metal into two paths to reduce non-uniformity in currents due to differences in length. Using an MRMP structure, we propose two new inductor designs for fan-out wafer-level packaging. A two-layer MRMP approach that implements the multi-path in an additional layer, and a one-layer MRMP configuration avoids the need for an additional layer by incorporating the multi-path in an inner turn. We compare inductance and quality performance according to the frequency of the two designs. When the MR technique is applied, the inductance increases due to the increase in the length of the inductor, but resistance also increases. As the frequency increases, alternating current (AC) resistance becomes dominant. The MP increases the quality factor by alleviating skin and proximity effects, which are the main causes of increased AC resistance. Analytical modeling is carried to rapidly estimate and optimize direct current inductance using partial inductance. To verify the improvement in efficiency due to the proposed inductor structure, we propose a prototype IVR that includes inductor loss and investigate the efficiency with circuit simulations using an IVR design with a conversion ratio of 3.6 V:1.8 V operating at 10 MHz. By using the two-layer MRMP inductor, the prototype IVR efficiency increases from 72.6% to 82.1%. A one-layer MRMP inductor, an IVR design with conversion ratio of 1.8 V:1.0 V and an operating frequency of 40 MHz, increases the maximum efficiency from 56.6% to 75.1%.

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## I. INTRODUCTION

As chip miniaturization accelerates, system-on-chip technology that integrates all
functions into one chip and system-in-package (SiP) technology that incorporates multi-chips
in a single package are the subject of active research ^{[1,}^{2]}. The degree of integration in power management integrated circuit (PMIC) blocks are
also being investigated. Among these block, existing converters have implemented large,
passive elements at the PCB level due to ripple currents, noise, and poor efficiency
^{[3,}^{4]}. As the size of electronic devices shrinks, technologies are being developed to regulate
and stabilize voltage output from the PMIC blocks and the passive elements required
for the regulator. Integrated voltage regulators (IVRs) enable high-speed micro-processors
to save power by switching frequencies more easily than is possible with conventional
converters ^{[5,}^{6]}. In addition, because the distance to the load can be relatively short, a small loop
can form, which is advantageous in a power delivery network (PDN). However, in an
IVR, the density involved in mounting an inductor in an area smaller than is typical
for existing converters can act as a bottleneck.

Due to the advent of packaging technology, such as inductor densification, additional
research has been conducted on inductor mounting locations and packaging type. Fig. 1. depicts the trend in inductor density and converters due to increased packaging
technology. In Fig. 1(a) the inductor and converter are integrated and mounted at the printed circuit board
(PCB) level. In the preceding trend, an inductor mounted on the interposer of the
chip to narrow the distance from the chip was developed as a board-embedded type,
as shown in Fig. 1(b). The interposer approach utilizes through-silicon via (TSV) technology to implement
a three-dimensional (3D) solenoid inductor, resulting in higher density ^{[7,}^{8]}. As the integration increases, the converter becomes a single chip, as illustrated
by Fig. 1(c), with an inductor embedded in the package. A structure in which the converter is
included in one chip and the inductor is used as a package-embedded type is shown
in Fig. 1(d). The major difference from the previous trend to chip design is that the process
of implementing a 3D inductor gives it the characteristic of an inductor using TSV
for a layer with a molding compound ^{[9,}^{10]}.

To improve the performance of the inductor, research on inductors has been conducted
in various fields. Spiral and solenoid types are used primarily to determine the structure
of the inductor. In a previous study on spiral inductors, the performance was increased
by using a thin film in a typical spiral inductor structure and partially wrapping
the metal line by placing a thin film on the top and bottom of the inductor in one
layer. The thin film used a magnetic material, and research to control performance
by changing the material properties of the magnetic material is in progress ^{[11-}^{13]}. In previous studies of mechanisms to change the structure of a spiral inductor,
a metal wire was divided into several paths in consideration of the depth of the skin
effect, or a spiral inductor with a tapered structure was used to change the thickness
of the central radius. Studies to improve alternating current (AC) resistance performance
have also been conducted ^{[14,}^{15]}. In previous studies in which the structure of the solenoid was not changed, a magnetic
thin film like spiral inductor was used to enhance performance or a magnetic core
was inserted into the center of the structure ^{[16,}^{17]}. However, embedding an inductor into a package or inserting a TSV into a molding
compound has little effect on the integration trend. A structure that compensates
for these shortcomings by adding multiple tiers in TSV based solenoidal inductor structures
has been proposed ^{[18]}.

This paper is organized as follows. Section II describes two design topologies for increasing inductor density — multi-radius and multi-path — and identifies design parameters. In section III, two new inductor design packages are proposed based on the concept of a ``multi-radius multi-path'' (MRMP) structure. To gauge performance, the inductance and quality of the two designs are evaluated according to frequency. In section IV, an analytical model for rapid estimation and optimization of DC inductance using partial inductance is assembled, and the model’s accuracy is compared with simulation results. Section V confirms the improvement in efficiency using the proposed inductor structure, a prototype IVR (including inductor loss) is designed, and the efficiency is investigated through circuit simulations. Section VI concludes the paper.

## II. MULTI-RADIUS MULTI-PATH STRUCTURE

First, to increase inductance, a turn is added in the direction of the increasing
magnetic flux, as shown in Fig. 2. This method, which can cause an increase in inductance without changing the area
and volume of the inductor, has been applied in a 3D integrated circuit structure
^{[18]}. We will call this multi-radius (MR) because adding outer and inner turns have different
radii. However, adding a turn increases direct current (DC) resistance by increasing
the conductor length, and AC resistance by reducing the distance between the conductors.
The AC resistance is dominated by skin and proximity effects. The skin effect causes
current to flow to the outside of the conductor as the frequency increases. The proximity
effect is a phenomenon in which the current density is concentrated to one side due
to the field effect between the conductors. Compared to typical converters, IVRs using
high frequency are more sensitive to AC loss.

Second, to minimize this increased resistance, we adopt the concept of multiple path
design proposed in ^{[21]}. Fig. 3 depicts the magnetic field change when current paths are divided. If there is a difference
in the length or thickness of the two metal lines, the non-uniform distribution of
current occurs due to the interaction of magnetic fields. At this time, by dividing
the existing paths, multi-path (MP), the field between the paths can be cancelled
out, and the magnitude of the current flowing through each path becomes relatively
small, which can alleviate uneven distribution of the current.

In this work, we proposed a new type of 3D solenoid inductor that can be implemented in redistribution layer in package. To increase inductance, additional turn is added, which we call MR technique. The major contribution of our work is applying the multi-path concept that was used in spiral inductors to 3D solenoid inductor in package. In a spiral inductor, the length of the red metal (the outer turn) is longer than that of the blue metal (the inner turn) as shown in Fig. 4(a). Because the general spiral inductor is implemented in a single layer, the spiral inductor for multi-path implementation must be divided to reduce the difference in lengths. In contrast, Fig. 4(b) presents a side view of the proposed MR solenoid inductor. Inductor structures with MR technology have different outer and inner winding lengths. No matter how close the two metals are, the essential structural features remain. It is difficult to reduce the difference in length compared with a line/space of several ${\mathrm{\mu}}$m in the spiral inductor due to the via generated during the implementation process. We proposed to use two layers in implementing MP. The concept is depicted in Fig. 5, in which the outer winding is thicker than the inner winding. When the outer path of the solenoid inductor is split, an additional via must be inserted. The outer winding has a high resistance because it goes through the via. To adjust the resistance value of the outer path, the outer winding is made thicker than the inner winding.

##### Fig. 3. A multiple-path structure to cancel magnetic fields: (a) current flowing in parallel directions; (b) each path divided into two.

## III. DESIGN EXAMPLES OF MRMP TECHNIQUE IN PACKAGE

This section examines the two types of inductors implemented in the package. All the proposed structures uses multi-radius multi-path (MRMP) technology introduced in the previous section. The difference in the two structures is whether the MP is implemented using one-layer or two-layer. Fig. 6 illustrates the two-layer MRMP structure that incorporates the inductor inside the redistribution layer (RDL), such as the package substrate of the SiP or the RDL interposer. This structure uses MR technology to increase inductance. In Fig. 6(a), the metal wire of the RDL is split to implement multi-path in two-layers, the red winding is the outer path, and the yellow winding is the inner path. The path is divided into upper and lower sections to accommodate the via. Fig. 6(b) shows the chip that is encapsulated with an epoxy molding compound (EMC). The RDL requires a layer for the inner winding, a layer for the path of the outer winding, and an additional layer for probing. Fig. 6(c) provides the approximate design parameters through a cross-section of an inductor. The term l represents the winding length of the inductor and h represents the simplified height of the via. The term lout is the length of the outer winding and l$_{\mathrm{in}}$ is the length of the inner winding. The value of h can be derived from the sum of the thicknesses used for each layer, and the smaller heights by connecting the layers. The term t is the thickness of the RDL line, which, as a result of multi-path implementation, can be divided through additional layers such that the inner turn structure must be implemented at the point where the molding compound reaches t$_{\mathrm{top}}$, t$_{\mathrm{bot}}$, and t$_{\mathrm{gap}}$. Due to design characteristics, an additional RDL is essential, and the probing layer is connected to the path of the outer winding. It is therefore necessary to further change the thickness of each layer, which can complicate fabrication. Fig. 7. shows one-layer MRMP structure that compensates for the usage of the additional RDL layer and can be implemented in the high-density package. In Fig. 7(a), while minimizing the area, MR is implemented with gray metal and MP using red metal. The most significant difference from the previous structure is the implementation of a MP approach. Including one layer of external windings in an orthogonal configuration has the advantage of utilizing the space between the routings and adding paths to this space. In addition, implementing multiple paths of internal rotation in this space increases the degree of integration. In the case of the two-layer MRMP structure, at least four additional RDLs are created for MRMP implementation. However, this structure can reduce the size of the two layers by using an extra RDL generated from the inner winding through a multi-path on the inner turn. Fig. 7(b) provides the design parameters set to implement MP in one-layer. The term l$_{\mathrm{sp}}$ is the distance between the outer winding and the inner winding and l$_{\mathrm{orth}}$ is the length of the lower routing implemented in an orthogonal form. The most significant difference from the two-layer structure is that line/space is set to a reasonable width. Fig. 7(c) provides the design parameters in the cross-section of the proposed structure. The design parameter selection is the same as that of the two-layer structure, but with a different height for the internal winding. The proposed inductor structures are summarized in the Table 1. Conventional structure is the typical solenoidal structure without the inner turn or multi-path implemented. Inductance and quality factors are vital parameters to evaluate the performance of an inductor. The main parameters are calculated using the Ansys high-frequency structure simulator (HFSS) tool to reflect the frequency characteristics. The quality factor is based on the ratio of the inductor’s loss and the preserved component over one cycle. This serves as an index of the overall performance of the inductor. It can be calculated as Q = 2${\pi}$f L/R, where f, L, and R are frequency, inductance, and resistance, respectively. This frequency-dependent formula can be applied to an IVR. The inductance and quality factor are defined by Eq. (1).

##### Table 1. Summary of proposed structures

Two-layer type |
Single radius |
Multi-radius (MR) |

Single path |
Conventional |
MR |

Multi-path (MP) |
- |
MRMP |

One-layer type |
Single radius |
Multi-radius (MR) |

Single path |
Conventional |
MR |

Multi-path (MP) |
- |
MRMP |

##### (1)

$ L=\frac{Im\left(1/Y_{11}\right)}{2\pi f}\\ Q=\frac{Im\left(1/Y_{11}\right)}{Re\left(1/Y_{11}\right)} $##### Table 2. Design parameters of the MRMP structure

##### Table 3. Key parameter comparison

Table 2 provides detailed design parameters of the proposed structures. Both structures are vertically symmetrical around the midpoint of the height. The thickness of the outer metal line was set to 10 ${\mathrm{\mu}}$m, and t$_{\mathrm{in}}$ and t$_{\mathrm{gap}}$ were set to 5 ${\mathrm{\mu}}$m to make a difference. The radius of the vias can be varied to increase performance but adding vias with different radii increases the process complexity. In implementing one-layer MRMP structure, the radii of the vias inside and outside are set to be the same. The two-layer MRMP structure constitutes an inner turn with half the value based on the outer RDL and via. A separate molding compound is not used because it is intended to be implemented inside the RDL layer. Table 3 summarizes the critical parameters of simulation data. For the previous inductance and quality factor, data were extracted using HFSS, and the DC resistance was confirmed using a Q3D extractor. The MRMP structure can relieve the increased resistance from 0.16${\Omega}$ to 0.13${\Omega}$ using a multi-path structure. The one-layer structure also showed the same pattern, but compared with the two-layer structure, fewer paths were added within a limited area, confirming from 1.1${\Omega}$ to 0.88${\Omega}$. Fig. 8. is the simulation result based on the design parameters. Fig. 8(a) depicts the inductance and quality factors according to frequency of a two-layer MRMP structure. All three cases have the same area, a metal width of 20 ${\mathrm{\mu}}$m was used. First, for conventional structure designed for two-layer structure, DC inductance produced the lowest value at 13.29 nH, and the self-resonance frequency (SRF) was 1.25 GHz. The value of Q$_{\mathrm{peak}}$ was 64.4, with the best loss characteristics. When the MR technology is added, DC inductance increased by 37.24% to 18.24 nH. As a trade-off for increasing routing, the quality factor was 26.46, a decrease of 59%. The value of the SRF near 0.5 GHz was confirmed by the increase in resistance. Lastly, for MRMP structure, the DC inductance was 18.4 nH, an increase of 38.45% compared with the conventional structure. In the case of the quality factor, a peak value of 40.4 can be obtained, an increase of 21.6% compared with the result with MR structure. It can be seen that the loss of energy corresponding to the denominator of the quality factor was significantly reduced due to the addition of the path. Fig. 8(b) depicts the inductance and quality factor according to frequency for three cases in a one-layer MRMP structure. Compared to the conventional structure significantly increased DC inductance by a factor of 2.55, from 1.98 nH to 5.58 nH, and the quality factor\textendash{}relieved Q$_{\mathrm{peak}}$ value increased by 12.8%, from 21.54 to 25.67, based on 32.16.

##### Fig. 6. Two-layer MRMP structure: (a) overall view; (b) cross-section view of implementation; (c) cross-section view with design parameters.

## IV. ANALYTICAL MODEL DERIVATION OF THE PROPOSED INDUCTOR

For quick inductance estimation, analytical modeling is done for one-layer structure. Inductance can be modeled separately as self-partial inductance and mutual-partial inductance of via and RDL winding layers. Self-partial inductance means the inductance of the wire itself, and mutual-partial inductance means the mutual inductance between two wires. The total inductance can be obtained by summing these two partial inductances, as shown in Eq. (2). Fig. 9 is a view of the one-layer MRMP structure for generalization of modeling. Fig. 9(a) is a top view and Fig. 9(b) is an isometric view. MATLAB software was used for the inductance modeling, and a 3D matrix was used to calculate the mutual inductance.

Fig. 10 provides the analytical parameters of RDL and via for self-partial inductance calculation. Fig. 10(a) shows the parameters required for calculating the inductance of an RDL conductor. The term l is the length of the RDL conductor t is the thickness of the conductor, and w is the width of the conductor. Fig. 10(b) is the parameter required to calculate the inductance of the via wire, where r is the radius of the via, and h is the height. Eq. (3) represents the sum of self-partial inductance and can be calculated by classifying RDL and via. RDL can express the entire RDL according to design parameters. N is the number of turns, and the RDL self-partial inductance of the one-layer MRMP structure can be expressed by Eq. (4). L$_{\mathrm{RDL}}$ is the inductance of RDL using l,w,t and is expressed as Eq. (5). All of the self-partial of RDL can be obtained through these processes.

##### (4)

$ S_{RDL}=2(N-1)L_{RDL}(l_{out},\,\,w,\,\,t_{out})\\ +L_{RDL}(l_{out}-w-l_{sp},\,\,w,\,\,t_{out})\\ +(2N-3)L_{RDL}(l_{orth}-w,\,\,w,\,t_{out})\\ +(2N-3)L_{RDL}(l_{out}-2l_{sp},\,\,w,\,\,t_{out})\\ +(2N-4)L_{RDL}(l_{in},\,\,w,\,\,t_{in})\\ +(2N-4)L_{RDL}(l_{orth}-w,\,\,w,\,\,t_{in}) $##### (5)

$ L_{RDL}(l,\,w,\,\,t)\simeq \frac{\mu l}{2\pi }\left[ln\left(\frac{2l}{w+t}\right)+\frac{1}{2}+\frac{w+t}{3l}\right] $Via self-partial inductance also has the same process as RDL. In the one-layer MRMP structure with N turns, the self-partial inductance of via is expressed by Eq. (6). The modeling difference from the RDL layer is that in the case of RDL, the thickness of RDL changes during the multi-path implementation process, but in the case of vias, the radius does not change. It can therefore be modeled more simply compared with RDL. L$_{\mathrm{via}}$is the self-partial inductance of the via and is expressed through Eq. (7) using r and h. Therefore, the self-partial inductance of the entire metal line can be obtained.

##### Table 4. Efficiency simulation set-up

##### (6)

$ S_{via}=(2N-1)L_{via}(h_{out},\,\,r_{via})\\ +2L_{via}(h_{in}+t_{in}+t_{gap},\,\,r_{via})\\ +(2N-5)L_{via}(h_{in},\,\,r_{via}) $##### (7)

$ L_{via}(h,\,\,r)=\frac{\mu l}{2\pi }\left[ln\right.\left(\frac{h}{r}+\sqrt{\left(\frac{h}{r}\right)^{2}+1}\right)\\ -\sqrt{\left(\frac{r}{h}\right)^{2}+1}+\frac{r}{h}+\frac{1}{4} $Mutual-partial inductance can be calculated using the Greenhouse formula ^{[20]}. The required parameters are the length of the RDL and the radius of the via and
the distance (d) between the two metals. The distance between all objects can be expressed
through an array by using a 3D matrix of MATLAB, as shown in Fig. 11. As both RDL and via are implemented in an orthogonal form, the one-layer structure
can be simplified by applying the assumption that there is no mutual-partial inductance.
As with the series-partial inductance, it can be calculated by dividing it into two
cases, RDL and via, and expressed as Eq. (8). The mutual partial inductance of RDL can be expressed through Eq. (9).

##### (8)

$M_{R D L}=\sum_{k=1}^4 \sum_{j=1}^{2 N}\left[\frac{1}{2}\left(G_{R D L}\left(l_j, d_{j k}\right)\right.\right.$

$M_{\text {total }}=M_{R D L}+M_{\text {via }}$

##### (10)

$ +\sum _{k=1}^{2}\sum _{i=1}^{2}\left[\frac{1}{2}\left(G_{RDL}\left(l_{orth},\,\,d_{ik}\right)+G_{RDL}\left(l_{orth},\,\,d_{ik}\right)\right)\right]\\ G_{RDL}(l,\,\,d)=\frac{\mu l}{2\pi }\left(\sinh ^{-1}\left(\frac{1}{d}-\sqrt{l^{2}+d^{2}}+d\right)\right) $The RDL is expressed in consideration of mutual inductance with different lengths, and RDL also has l$_{\mathrm{orth}}$ orthogonal to l$_{\mathrm{out}}$, l$_{\mathrm{in}}$, which can be calculated by separating them into two terms using their offset. G$_{\mathrm{RDL}}$ is the same as in Eq. (10) using the Greenhouse formula to express the mutual inductance of the RDL layer. Via’s mutual-partial inductance proceeds in the same process as RDL and can be expressed by Eq. (11). This includes the outer and inner via heights in the structure of the one-layer MRMP structure. G$_{\mathrm{via}}$ is the formula applied to vias by the Greenhouse formula, and is

##### (11)

$ M_{via}=\sum _{j=1}^{N-1}\sum _{i=1}^{4}\left[\frac{1}{2}(G_{via}(h_{i},\,\,d_{ij})\right.\\ +G_{via}(h_{j},\,\,d_{ij}))-G_{via}(h_{i}-h_{j},\,\,d_{ij}) $##### (12)

$ G_{via}\left(h,\,\,d\right)=\frac{\mu h}{2\pi }\left[ln\left(\frac{h}{d}+\sqrt{\left(\frac{h}{d}\right)^{2}+1}\right)\right.\\ \left.-\sqrt{\left(\frac{d}{h}\right)^{2}+1}+\frac{d}{h}\right] $the same as Eq. (12), where h is the height of the via, and d is the distance between two vias. All inductances
can be expressed through the following modeling, and calculations can be performed
by generalizing turns. The accuracy can be assessed by comparing the formulas subjected
to analytical modeling and simulation results ^{[22]}. In Table 1, the lengths l$_{\mathrm{out}}$, l$_{\mathrm{orth}}$, and h$_{\mathrm{via}}$ of the
inductors most closely related to performance among inductor design parameters were
compared and veriﬁed. As shown in Fig. 12(a), the standard h$_{\mathrm{via}}$ was 200 ${\mathrm{\mu}}$m. Compared to the conventional
inductor structure, the MR structure and the MRMP structure make it possible to realize
a large inductance that is more than twice as strong. In addition, the inductance
increases and decreases with almost the same slope in response to the change of h$_{\mathrm{via}}$
in the comparison between the inner turn structure and the MRMP structure (Fig. 9). In Fig. 12(b), l$_{\mathrm{orth}}$was implemented as 25 ${\mathrm{\mu}}$m and the MRMP structure
had an error of about 0.4%, with 7.8 nH for mathematical modeling and 7.78 nH for
the simulation. In the case of Fig. 12(c), the mathematical modeling of the MRMP structure was 7.48~nH, and the simulated value
was 8.21 nH, with an error of approximately 8.4%. This approach offers the advantage
of checking the value of DC inductance more rapidly than the simulation using analytical
modeling.

## V. INDUCTOR DESIGN FOR IVR EFFCIENCY OPTIMIZATION

In this section, the efﬁciency of the IVR according to the structure of the inductor
proposed in this work is evaluated through a simulation. An advanced design system
simulation tool was used to check the efﬁciency ^{[23]}. Fig. 13 is a schematic diagram of a prototype IVR. M$_{\mathrm{n}}$ and M$_{\mathrm{p}}$
used Berkeley short-channel insulated-gate ﬁeld-effect transistor model 4 (BSIM4)
with a gate length of 90 nm ^{[24]}. Changes in efﬁciency according to the performance of the inductor itself were evaluated
using a prototype IVR with an ideal pulse equal to the switching frequency serving
as the input of the switch, and the effect of power delivery network loss were not
reﬂected. Table 4 shows the IVR settings of the two-layer inductor structure and one-layer inductor
structures. For the two- layer inductor structure, a potential of 3.6 V was applied,
and the desired output voltage was set to 1.8 V. The MOSFET has a switching frequency
of 10 MHz and an output capacitance of 30 nF. The one-layer inductor structure has
an input potential of 1.8 V and an output voltage of 1.0 V. The output capacitance
is 220 nF and the switching frequency is set to 40 MHz.

##### (13)

$ \eta =\frac{P_{out}}{\left({I_{out}}^{2}\right)\times \left(R_{L}+R_{PDN}+R_{ds}\right)+P_{switching}} $Efficiency can be expressed by Eq. (13), where P$_{\mathrm{out}}$ is the power consumption of the logic, R$_{\mathrm{L}}$ is the resistance component of the inductor, R$_{\mathrm{ds}}$ is the resistance value between the drain, the power MOSFET is the source, and P$_{\mathrm{switching}}$ is the switching loss of the MOSFET. This variable has P$_{\mathrm{out}}$ set and is ignored. Fig. 14. shows the efficiency data according to the load current using the inductor of the proposed structure. Fig. 14(a) supplies the efficiency data of the two-layer MRMP structure. As a result of checking the efficiency for the three cases of conventional structure, inner turn, and MRMP, the maximum value of efficiency was determined to be 72.6% for the conventional structure, with both multi-radius and multi-path added, for an efficiency increase of 9.5% to 82.1%. Fig. 14(b) shows the efficiency data of the one-layer MRMP structure, which exhibited a low value of 56.6% in the case of the conventional structure and increased by 15% to 71.6% in the process of adding inner turns. In addition, it is confirmed that the efficiency of MRMP structure is 75.1%, which is 18.5% greater than that of the conventional structure. The reduction in the loss of the inductor itself through the efficient control of the ripple current through the higher inductor and the increase of the quality factor of the inductor through the multi-path in the process of using the inner turn had a major influence on efficiency.

## V. CONCLUSIONS

An MRMP structure incorporating high-density inductors was proposed to improve the performance of IVR. By applying the multi-turn technique, the inductance was increased, and the multi-path technique alleviated the resistance increase. Based on the concept of MRMP structure, two inductor structures are proposed: a type that implements a MP concept using two layers, and another structure that does not use an additional layer by implementing a MP using one layer. Also, a method to quickly check DC inductance through mathematical modeling has been added. As a result of simulating the efficiency considering the specifications of IVR using two inductor structures, both the two-layer MRMP structure and the one-layer MRMP structure showed improvement in efficiency. The proposed inductor-design technique can be applied to various packaging types to increase the inductor’s performance to improve the efficiency of the IVR.

## ACKNOWLEDGMENTS

This work was supported by Samsung Electronics Co. Ltd. (No. IO20120907919-01) and the National Research Foundation of Korea grant funded by the Korea government (MSIP) (NRF-2020R1A2C1011831, No. 2020M3H2A1076786). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.

## References

GiWon Kim received the B.S. degree in Electronic Engineering from College of Electronics & Information of Kyung Hee University in 2019. He is currently pursuing Ph.D. degree in the Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea. His current research interests include IC and package design, signal and power integrity, and electromagnetic compatibility.

SoYoung Kim received a B.S. degree in Electrical Engineering from Seoul National University in 1997, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1999 and 2004, respectively. From 2004 to 2008, she worked for Intel Corporation, Santa Clara, CA, and from 2008 to 2009, she worked for Cadence Design Systems. She is a Professor in the Department of Semiconductor Systems Engineering of the College of Information and Communication Engineering of Sungkyunkwan University. Her research interests include VLSI computer aided design, signal integrity, power integrity and electromagnetic interference in electronic systems.