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  1. (Electronic Engineering, Gachon University, Seongnam, Gyeonggi-do, 13120, Korea)

Ultra shallow LDD junction, solid phase diffusion, field extended source/drain, local interconnection


In order to increase the ULSI circuit performance, the device shrinkage into submicron regime and the higher packing density is highly required. As the size of the MOSFET is scaled down, the junction depth of the source/drain should be decreased to reduce the short channel effect (1-4). The shallow junction formation and the silicidation on the shallow junction are essential in obtaining the high performance of submicron devices. However it is difficult to achieve it by conventional technique such as low energy ion implantation and rapid thermal annealing (RTA). To reduce parasitic resistance, abrupt dopant profile and high electrical activation are required. Several technologies have been proposed to obtain an ultra-shallow junction (5-9). Of those, special efforts for achieving low thermal budget formation of ultra-shallow junctions have been made. Another challenging problem is a silicidation of the ultra-shallow junction for achieving a low sheet resistance of the ultra-shallow source/drain region because a direct silicidation on the ultra-shallow junction has been usually impractical due to a Si consumption phenomena resulting in a leakage current.

In this study, we present three novel process ideas to obtain above requirements in current trend. The key ideas are (1) the ultra-shallow junction formation by using SPD (Solid Phase Diffusion) through ‘amorphous Si (a-Si) / thin oxide’ layer, (2) the silicidation using SES (Selectively Etched a-Si) formed over the source/drain which can avoid a consumption of the original Si substrate, and (3) TiSi$_{2}$ local interconnection approach which can be obtained by itself as a by-product of above process.

All these ideas have been successfully verified by the fabrication of PMOSFET with 0.76 μm gate length. The schematic structure of the pMOSFET consisting of these novel processes is shown in Fig. 1 and a layout example for a RAM circuit is shown in Fig. 2. The local interconnection scheme with minimum geometry source/drain junctions can be used to increase the packing density of sub-micrometer ULSI circuits and to reduce parasitic capacitance.

Fig. 1. The schematic structure of the pMOSFET with the LDD (Lightly Doped Drain) formed by a SPD (Solid Phase Diffusion) technology and a Ti-silicided FESD (Field-Extended Source/Drain).


Fig. 2. Example of the local interconnect as used in as RAM cell (N. H. E. Weste, “Principles of CMOS VLSI DESIGN}”, p.133).


Fig. 3. The process flow for the application of SPD (Solid Phase Diffusion) method through $^{\prime}$a-Si / Thin Barrier Oxide$^{\prime}$ Layer to the LDD (lightly doped source/drain) of pMOSFET (a) gate definition and SPD, (b) wet oxidation, (c) side-wall oxide formation by RIE.


II. Experimental Details

For the ultra-shallow junction, a solid source of B$_{2}$O$_{3}$ has been driven into a single crystal Si substrate through 'amorphous Si / thin oxide' layer, where the amorphous Si (a-Si) layer plays a role as a boron sorption layer and a thin oxide as a diffusion barrier and simultaneously piling-up region of B atoms. Then, the deposited a-Si layer is converted into an oxide layer during wet oxidation.

The process flow for the application of this SPD method to pMOSFET is shown in Fig. 3. The starting substrate was n-type, (100) Si wafers with a resistivity of 10${\sim}$15 Ω-cm. Gate oxide thickness was 8 nm and the p$^{+}$ poly Si gate of 2,500 Å was defined with PSG (Phosphosilicate Glass) oxide of 6,500 Å. Then, thin oxide as a diffusion barrier was thermally grown 7 nm or 9 nm in dry oxygen ambient at 850 $^{\mathrm{o}}$C. Subsequently, a-Si layer was deposited 45 nm by LPCVD at 560 $^{\mathrm{o}}$C. And, boron atoms were diffused into ‘a-Si / thin barrier oxide’ layer from B$_{2}$O$_{3}$ solid source wafers as in Fig. 3(a). As in Fig. 3(b), the B-doped a-Si layer was fully converted into an oxide layer during wet oxidation for 30 min at 850 $^{\mathrm{o}}$C. As shown, the p$^{-}$ layer formed by SPD is used as the ultra-shallow junction under the side-wall oxide which makes so-called a LDD (Lightly Doped Drain) region. In the next step, vertical etching of the oxide layer is done by RIE (Reactive Ion Etching) process which can remain the side-wall oxide of the poly-Si gate with PSG as shown in Fig. 3(c). Through this technology, we can obtain the thermally grown side-wall oxide with the quality much better than any others (APCVD, TEOS, HTO, etc.).

III. Results and Discussion

First of all, we have found out the SPD drive-in temperature condition in order to obtain a proper sheet resistance value for the extended p$^{-}$ region of the source/drain. Through the experiments on the sheet resistance variations with diffusion temperature, we have selected 850 C as the proper drive-in conditions.

Fig. 4 shows the SIMS depth profiles of the boron atoms driven into 'a-Si / thin oxide / Si sub.' samples. Thin barrier oxide was grown by thermal oxidation (profiles a, b) for 10 min at 850 C in a pure oxygen furnace or by the boiling in H$_{2}$SO$_{4}$ solution for 10 min at 120 $^{\circ}$C (profile c) before the deposition of a-Si of 450 Å. In the profile d, any native oxide was removed just before a-Si deposition.

We can see that the ‘a-Si / Si sub’ interface with a thin oxide plays the roles of good diffusion barrier and piling-up of boron atoms. Both the cases of 70 and 90 Å oxide interface layer have no difference in the boron profiles. And, the oxide (about 30 Å) by boiling in H$_{2}$SO$_{4}$ also plays considerably a role of diffusion barrier compared to the sheet-off case of native oxide but allows diffusing the boron atoms into the substrate a little more than those of 70 and 90 Å oxide layer. After driven-in the boron atoms, the B-sorbed a-Si layer (400 Å) was converted into an oxide layer (about 1,000 Å) during wet oxidation for 30 min at 850 C and used as a side-wall oxide in the gate structure of MOSFET through RIE process.

Fig. 4. SIMS depth profiles of the boron atoms diffused into Si substrate through $^{\prime}$a-Si / thin oxide$^{\prime}$ layer from B$_{2}$O$_{3}$ solid source. SPD was performed for 30 min at 850 $^{\circ}$C.


Fig. 5. SIMS depth profiles of the boron redistributed during the wet oxidation of the a-Si layer. Wet oxidation was performed for 30 min at 850 $^{\circ}$C.


Fig. 5 shows SIMS profiles of the boron atoms redistributed during wet oxidation of the a-Si layer. As shown in the figure, the redistribution within Si substrate has not occurred during wet oxidation. The junction depth in profiles 'a' and 'b' was about 30 nm and the surface concentration was about 3${\times}$10$^{19}$ cm$^{-3 }$which could be a sufficient value for a LDD region.

The thickness values of the oxide layers grown during wet oxidation in the different sample conditions were measured and compared. The thickness grown in ‘B-doped a-Si / Si substrate’ was 1,034 Å, while those in ‘boron diffused Si-substrate without a-Si’ and ‘just bare Si without B diffusion’ were 634 Å and 545 Å, respectively. The oxidation rate of the B-doped a-Si layer was about 1.9 times higher than that of the bare Si, which indicates that the selective oxidation of B-doped a-Si layer can be easily obtained.

In order to fabricate a pMOSFET using this technology, we have followed the process steps as shown in the Fig. 6. The p$^{\mathbf{{-}}}$ layer formed by SPD is used as the ultra-shallow junction under the side-wall oxide. In addition, through this technology, we can obtain the thermally grown side-wall oxide with the quality much better than any other (APCVD, TEOS, HTO, etc.). Right after making the side-wall oxide by RIE, amorphous Si layer was deposited again 40 nm by LPCVD. Then, BF$_{2}$$^{+}$ ions were implanted through the pre-deposited a-Si layer for making p$^{\mathbf{+}}$ source/drain regions and RTA was followed to anneal the implanted boron atoms, as shown in Fig. 6(a). Then, in order to make remove selectively the a-Si layer only on the gate, an etch-back process using photoresist was performed as in Fig. 6(b)-(d). After the PR strip, a-Si layer on field region was patterned using another mask which could be designed to be elongated on the field region as a local interconnect. The a-Si layer is completely consumed during Ti-silicidation. Therefore, the consumption of the original Si substrate in the source/drain area can be avoided and self-aligned silicidation process (SALICIDATION) can be implemented by itself (10-13). Then, a contact area was formed on the field region, as shown in Fig. 6(e).

Fig. 6. Process flow for the formation of a pMOSFET right after making the p$^{{-}}$ LDD as shown in Fig. 3(a) a-Si deposition, BF$_{\mathrm{2\-}}$$^{+}$ implantation and RTA, (b) P.R. coating, (c) P.R. etch-back, (d) a-Si etch-back, (e) a-Si patterning with FESD mask, PSG removal in HF, Ti-deposition, silicidation and contact mask.


Fig. 7. Photographs of the top views for the fabricated (a) FESD structure, (b) conventional structure MOSFETs. In the FESD structure, in which contact is formed on the TiSi$_{2}$ layer extended over field region, the length of S/D is 2.0 μm, but in conventional structure, the S/D length is 5.5 μm when designed with same design rule.


Another feature in this study is to develop the process technology with a much more scale-downed source/drain width compared with the conventional process without sacrificing the sheet resistance and the contact resistance. We call it “FESD (Field Extended Source/Drain)” technology. This FESD layer can be also used as a local interconnection. That is, the contacts to the source/drains can be formed on the FESD above the field oxide area but not on the active area. Thus, the effective active area can be reduced by the contact areas. Resultantly, the junction capacitance could be reduced, which also would be helpful to accelerate the switching speed.

The photos about the layout of the pMOSFET fabricated using this technology is shown in Fig. 7(a), with comparing the layout (Fig. 7(b)) of the pMOSFET formed by a conventional technology. By using this technology, the physical design width of active area could be shrunken 2.75 times as a conventional structure with same design rule.

The successful gate structure formed according to the schematics is shown in Fig. 8. The side-wall on the gate-side and the Ti-silicided source/drain layer extended over the field oxide are clearly shown. We can see that the physical design area of the active mask was reduced prominently through the FESD structure.

Fig. 8. SEM cross-section view of the MOSFET with Ti-silicided FESD and thermal side-wall oxide (a) 20,000 times, (b) 5,000 times magnified.


Fig. 9. I$_{\mathrm{d}}$-V$_{\mathrm{d}}$ characteristics of the FESD-type pMOSFET with the contact on field oxide region.


Fig. 10. Subthreshold characteristics of the FESD-type pMOSFET with the contact on field region.


Using above technologies, we have fabricated the pMOSFET with effective gate length of 0.76 μm. The I$_{\mathrm{d}}$-V$_{\mathrm{d}}$ characteristics are shown in Fig. 9 and the subthreshold characteristics in Fig. 10. The subthreshold swing is about 96 mV/dec and the maximum transconductance is 352 μS at V$_{\mathrm{g}}$=-3.1 V. Drain-induced barrier lowering (DIBL) of the fabricated FESD-type pMOSFET is 25.3 mV/V assuming that the threshold voltage is extracted by the constant current method at I$_{\mathrm{d}}$ = 10$^{-7}$ A/μm and even smaller value of 11.2 mV/V is obtained if the reference I$_{\mathrm{d}}$ is relaxed to 10$^{-8}$ A/μm.

This technology requires some additional processes such as a-Si deposition and PR/a-Si etch-back, and also another mask for implementing the FESD layout. However, these processes are not stringent and conventional. Therefore, for the practical usage, it will be necessary to consider a trade-off between some processing complexity and chip scalability/device speed. In addition, some process modification may be necessary in order to apply this technology independently with nMOSFET for CMOS circuitry.


We have developed novel process technologies to acquire the breakthrough in a deep sub-micron device regime. Through the SPD, ultra-shallow p$^{-}$n junction of 30 nm depth was obtained and a thermal side-wall oxide could be formed simultaneously. By using the Ti silicidation of selectively etched a-Si layer, the local interconnect with the contacts formed on field region could be easily obtained, not resulting in the Si consumption on the source/drain area during silicidation.


This research was funded and conducted under「the Competency Development Program for Industry Specialists」of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. P0012453, Next-generation Display Expert Training Project for Innovation Process and Equipment, Materials Engineers).


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Eou-Sik Cho

received the B.S., M.S. and Ph. D degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea in 1996, 1998, and 2004, respectively.

From 2004 to 2006, he was a senior engineer with the Samsung Electronics, where he worked on the process development of large size TFT-LCD. Since 2006, he has been a member of the faculty of Gachon University(Seongnam, Korea), where he is currently an Professor with the Department of Electronic Engineering.

His current research interests include fabrication process of semiconductor and display device, OLED display manufacturing and its application, laser application of transparent electrode and semiconductor film, flexible substrate.

Sang Jik Kwon

received the B.S., M.S. degrees from the Department of Electronics Engineering at Kyungpook National University, Daegu, Korea, in 1985 and 1991, respectively, and received the Ph.D. degree from the Department of Electronics Engineering at Seoul National University in 1991.

He worked as a research scientist at Electronics and Telecommunications Research Institute (ETRI) from 1983 to 1988, where he worked on MOSFET and power devices.

From 1988 to 1992, he worked as a research assistant at the Inter-university Semiconductor Research Center (ISRC) where multi-process chip (MPC) and ion implantation techniques were developed.

He joined Gachon University as a professor in 1992. His research interests include semiconductor devices, OLED display simulation and manufacturing, transparent electrode, thin-film compound solar cell, carbon nanotube applications, and related processing technologies.