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1. (School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, 702-201, Korea.)
2. (Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongju 38180, Korea)
3. (Power Semiconductor Research Center, Korea Electrotechnology Research Institute, Changwon 51543, Korea)

Gallium nitride, vertical device, power device, boost converter, breakdown voltage

## I. INTRODUCTION

Since gallium nitride (GaN) has superior material properties such as high breakdown electric field and high electron saturation velocity, make GaN-based transistors attractive for high-power and high frequency applications (1-4). Specifically, AlGaN/GaN high electron mobility transistors (HEMTs) have been designed for high-power radio-frequency (RF) devices due to the high-density two-dimensional electron gas (2-DEG) obtainable from AlGaN/GaN heterojunction (5-8).

The GaN-based power devices demonstrated improved electrical performances, such as large on currents and high breakdown voltages (9-12); such advancements are essential in systems with high power consumption. Furthermore, when developing autonomous driving systems based on electric vehicles, which have recently attracted considerable attention, power devices are considerably important because of their application in various devices, including the internal electric system, motor drive, and wireless battery charging system. According to the SAE J2954 standard released in 2017, wireless charging of electric vehicles requires a high power of approximately 11 kW; hence, devices capable of high-voltage/-current operation are required (13,14). Therefore, a wireless charging system for autonomous driving systems requires a device that can handle an ultrahigh power of greater than 11 kW; hence, the device must exhibit a high breakdown voltage and improved power characteristics. This can be achieved by increasing the operating current when the width of the existing GaN-based devices is increased and the gate-to-drain length (L$_{\mathrm{GD}}$) is increased to obtain a device with a high breakdown voltage.

However, these methods exhibit low integration because of the large device size. Therefore, it is essential to develop a vertical device that can increase the breakdown voltage without increasing the surface area of the device. In addition, a very short gate length is required to increase the amount of current flowing, which can cause a short channel effect. However, in the case of a vertical device, a long gate length and a large breakdown voltage can be obtained without increasing the device area. Additionally, since the proposed device is a GaN-based device, it has sufficient durability against temperature rise due to high output. The most suitable substrate for manufacturing a vertical device is a GaN-on-GaN substrate (19-23), which has the advantage of making a high-performance power device using the back side contact, but has a problem of high cost. Therefore, in this study, we designed a vertical GaN power device based on GaN-on-sapphire, which can manufacture vertical devices at low cost, and analyzed the operation of the boost converter using it. The vertical GaN power devices are optimally designed based on their primary DC characteristics, and the performances of the boost converter based on these devices were analyzed through device{--}circuit mixed-mode simulations. The proposed vertical GaN power devices exhibit high on current and breakdown voltage. Additionally, the boost converter obtained using such devices exhibits high voltage conversion efficiency.

## II. Device Structure and Simulation Strategies

Fig. 1 shows the structure of the simulated vertical GaN power device. The proposed device has a double-gate structure in which a gate can be observed at the side wall of the fin after the GaN epitaxy is etched into a fin shape. The gate length (L$_{\mathrm{G}}$) of the simulated device is 900 nm. Al$_{2}$O$_{3}$ is the dielectric material of the gate, and its thickness (T$_{\mathrm{ox}}$) is 15 nm. The gate-to-source length (L$_{\mathrm{GS}}$) is 300 nm. The gate-to-drain length (L$_{\mathrm{GD}}$) is 30 μm. The fin height (H$_{\mathrm{fin}}$) is 1 μm and the fin width (W$_{\mathrm{fin}}$) is 200 nm. These design parameters of device in this study are summarized in Table 1. The doping concentration of source, channel, and drain regions are n$^{+}$ 3${\times}$10$^{18}$ cm$^{-3}$, n$^{-}$ 1${\times}$10$^{15}$ cm$^{-3}$, n$^{+}$ 3${\times}$10$^{18}$ cm$^{-3}$, respectively. Threshold voltage (V$_{\mathrm{th}}$) is defined as the gate voltage (V$_{\mathrm{GS}}$) when the drain current (I$_{\mathrm{D}}$) is 1 mA/cm$^{2}$ via the constant-current method. The on current of the saturation current (I$_{\mathrm{on}}$) is defined as I$_{\mathrm{D}}$ when V$_{\mathrm{GS}}$ = drain voltage (V$_{\mathrm{DS}}$) = V$_{\mathrm{DD}}$ = 7 V. The off current (I$_{\mathrm{off}}$) is defined as I$_{\mathrm{D}}$ when V$_{\mathrm{GS}}$ = 0 V. The subthreshold swing (SS) is defined as the inverse of the highest slope between two points (V$_{\mathrm{GS}}$, I$_{\mathrm{D}}$) in the subthreshold region. Simulations were performed by assuming that the source and drain are ideal ohmic contacts. The drive voltage (V$_{\mathrm{DD}}$) is set to 7 V. Additionally, the reliability of simulations has been improved by using multiple physics models. First, we considered the defects that may occur inside the GaN material during the GaN growth process and the interface trap between GaN and oxide. Second, low-field- and high-field-mobility models are applied to evaluate the mobility of the proposed device. This model can accurately calculate the change in mobility owing to the heat caused by the scattering of carriers in a high-voltage operation. Finally, the field-dependence mobility model was applied to analyze the mobility in a high field. Thus, various models were used to achieve a reliable simulation, and a DC/DC boost converter was designed using the proposed device.

Fig. 1. The vertical GaN power device structure.

Table 1. The design parameters of vertical GaN power device

Fig. 2. Schematic of the process flow for the vertical GaN power device.

Possible process architecture for the vertical GaN power device can be suggested and presented as shown in Fig. 2. First, a nickel metal serving as a source contact is deposited on the grown GaN-on-sapphire substrate, and fins are formed using this as a mask.

Second, it forms a drain ohmic contact on the outside and covers the entire device with oxide. Second, it forms a drain ohmic contact on the outside and covers the entire device with oxide. After that, an etch-back process is used to form a SiO$_{2}$ layer and additionally deposit gate metal and oxide. Finally, a PR mask is formed using an etch-back process, and then a gate is formed through an etching process.

Fig. 3. (a) Breakdown voltage according to gate length without bottom undoped GaN layer, (b) Breakdown voltage characteristics with or without bottom undoped GaN layer.

## III. Results and Discussion

Fig. 3(a) shows the breakdown voltage as a function of gate length for a vertical device without a bottom undoped GaN layer. The figure shows it has a very low breakdown voltage of 60 to 101 V, and devices with this performances cannot be used in power circuits. This low breakdown voltage value is caused by a sharp increase in the field where the gate is vertically bent at the boundary between the fin and n-type GaN layers. Therefore, it is necessary to disperse the field, to improve the breakdown voltage, and for this purpose, a bottom undoped GaN layer is applied. Fig. 3(b) shows the breakdown voltage characteristics depending on the bottom undoped layer.

The figure, when the bottom undoped layer is applied, the breakdown voltage is greatly improved from 101 V to 1693 V. This is because, in the absence of an undoped GaN layer in the proposed device, a thin oxide thin film under gate forms a high electric field in the oxide and n$^{+}$ GaN layers. However, the presence of an undoped GaN layer at the bottom has a relatively low electron concentration compared to the n$^{+}$ GaN layer, so the added layer adequately dissipates the high electric field generated by the drain voltage. Fig. 4 shows the DC characteristics of the proposed vertical GaN power device. The proposed device has a V$_{\mathrm{th}}$ of 0.78 V and a very high on-current of 22 kA/cm$^{2}$. I$_{\mathrm{off}}$ shows a very low value of 413 pA/cm$^{2}$, and SS is 70 mV/dec. Therefore, the proposed device has been confirmed to have high operating current, high breakdown voltage, and low I$_{\mathrm{off}}$, making it a suitable device for the DC/DC boost converter design discussed in this study. Additionally, as shown in Fig. 5, the amount of gate charge was checked to confirm the switching characteristics of the proposed device. The total gate charge (Q$_{\mathrm{g}}$) is the amount of charge that must be injected into the gate electrode to turn on (drive) the device. The units of Q$_{\mathrm{g}}$ are coulombs (C), and if the total gate charge is large, it takes time to charge the capacitor needed to turn on the device, thus increasing the switching losses. The lower the value, the lower the switching losses and the higher the achievable switching speed. In Fig. 5, the drain side supply voltage (V$_{\mathrm{DD}}$) and drain current (I$_{\mathrm{DS}}$) are fixed, and the minimum amount of charge necessary for I$_{\mathrm{DS}}$=20 μA/mm current flow is 2.31 pC. At this time, the V$_{\mathrm{GS}}$ is 0.33 V. A power device’s switching loss and conduction loss are important factors to consider when reducing power loss. Among them, the switching loss is determined by the Q$_{\mathrm{g}}$ (15-18). Therefore, in the structure design that can reduce the switching loss of the power MOSFET, the greatest effect can be seen by reducing the charge in the gate region. This 2.08 pC showed very good performance.

Fig. 4. DC characteristics of vertical GaN power device.

Fig. 5. Gate charge of vertical GaN power device.

Fig. 6. Circuit diagram of the designed DC/DC boost converter.

Table 2. Design parameters of the designed boost converter

Fig. 7. The input and output voltage curves associated with the switching time of the designed boost converter.

Fig. 6 shows the circuit diagram of the designed DC/DC boost converter. The input voltage is 1000 V, and the switching frequency of the transistor and duty cycle are 1 MHz and 0.5, respectively; thus, a circuit with an output voltage of 2000 V is designed. Table 2 shows the detailed design parameters (24).

Fig. 7 shows the input and output voltages of the designed DC/DC boost converter. The circuit can operate even when the input voltage is 1000 V using a transistor having a high breakdown voltage. With this converter, an input voltage of 1000 V results in an output voltage of 1955 V, denoting a voltage conversion efficiency of 97.75%.

## IV. CONCLUSIONS

In this study, a vertical GaN power device based on GaN-on-sapphire epitaxy was designed. A DC/DC boost converter was constructed using this device and its characteristics were analyzed. The reliability of the simulation was improved using a bulk trap inside GaN and an Al$_{2}$O$_{3}$/GaN interface trap, and the lattice temperature model and low-field-mobility model developed by Albrecht et al. were used to obtain the self-heating effect. The designed vertical GaN power device exhibited excellent DC characteristics, with an I$_{\mathrm{on}}$ of 22 kA/cm$^{2}$, I$_{\mathrm{off}}$ of 413 pA/cm$^{2}$, and SS of 70 mV/dec. The designed device had a high breakdown voltage of 1693 V. In addition, a DC/DC boost converter was designed to double the input voltage of 1000 V using the proposed device. The designed boost converter produced an output voltage of 1955 V, with a voltage conversion efficiency of 97.75 %.

### ACKNOWLEDGMENTS

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2020R1A2C1005087). This study was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966), by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for developing the future semiconductor devices. This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2021R1A6A3A13039927). This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2021M3F3A2A03017764). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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## Author

##### Min Su Cho

Min Su Cho received a B.Sc. degree in computer engineering from the College of Electrical and Computer Engineering, Chungbuk National University (CBNU), Cheongju, South Korea, in 2015, and an M.Sc. degree from the School of Electronics Engineering (SEE), Kyungpook National University (KNU), and Ph.D. degree in Electronics Engineering from the School of Electronic and Electrical Engineering.

He is currently postdoctoral researcher with KNU.

His research interests include the design, fabrication, and characterization of compound CMOS, tunneling FETs, and III–V compound transistors.

##### Sang Ho Lee

Sang Ho Lee received the B.Sc. degree in electronics engineering from the School of Electronics Engineering (SEE), Kyungpook National University (KNU), Daegu, South Korea, in 2019, where he is currently pursuing the Ph.D. in School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea.

His research interests include the design, fabrication, and characterization of gate-all-around logic devices and capacitor-less 1T-DRAM transistors.

##### Hee Dae An

Hee Dae An received the B.Sc. degree in School of Electronic Engineering, Kumoh National Institute of Techology (KIT), Gumi, South Korea, in 2019, where he is currently pursuing the M.Sc. degree in School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea.

His research interests include the design, fabrication, and characterization of capacitor-less 1T-DRAM transistors and vertical GaN power devices.

##### Jin Park

Jin Park received a B.Sc. degree in electronic engineering from the School of Electronics Engineering (SEE), Kyungpook National University (KNU), Daegu, South Korea, in 2020, where she is currently pursuing the M.Sc. degree in School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea.

Her research interests include the design, fabrication, and characterization of gate-all-around logic devices and capacitor-less 1T-DRAM transistors.

##### So Ra Min

So Ra Min received the B.Sc. degree in Electronic Engineering from the School of Electronics Engineering, Yeungnam University (YU), Gyeong-san, North Gyeongsang, South Korea, in 2020, where she is currently pursuing the M.Sc. degree in school of Electronic and Electrical Engineering.

Her research interests include the design, fabrication, and characterization of GaN devices and capacitor-less 1T-DRAM transistors.

##### Geon Uk Kim

Geon Uk Kim received a B.Sc. degree in electronic engineering from the School of Electronics Engi-neering (SEE), Kyungpook National University (KNU), Daegu, South Korea, in 2021, where he is currently pursuing the M.Sc. degree in School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea.

His research interests include the design, fabrication, and characterization of GaN devices and capacitor-less 1T-DRAM transistors.

##### Young Jun Yoon

Young Jun Yoon received the B.S. and Ph.D. degrees in electronics engineering from Kyungpook National University, Daegu, Korea, in 2013 and 2019, respectively.

He is currently postdoctoral researcher with Korea Multi-purpose Accelera-tor Complex, Korea Atomic Energy Research Institute (KAERI).

His research interests include design, fabrication, and characterization of logic transistor and memory.

##### Jae Hwa Seo

Jae Hwa Seo received the B.S. and Ph.D. degrees in Electronics Engi-neering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2012, 2018.

He worked as a Post Doc. in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2018 to 2019.

Now, he has worked as reseacher at Power Semiconductor Research Center, Korea Electrotechnology Research Institute.

His research interests include the design, fabrication and characterization of V-NAND/1T-DRAM devices, nano-scale CMOS, tunneling FETs, and compound/silicon based transistors.

##### In Man Kang

In Man Kang received the B.S. degree in electronic and electrical engineering from School of Electronics and Electrical Engi-neering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D. degree in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2007.

He worked as a teaching assistant for semiconductor process education from 2001 to 2006 at Inter-university Semiconductor Research Center (ISRC) in SNU.

From 2007 to 2010, he worked as a senior engineer at Design Technology Team of Samsung Electronics Company.

In 2010, he joined KNU as a full-time lecturer of the School of Electronics Engineering (SEE).

Now, he is currently working as a professor.

His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistor, low-power nano CMOS, and III-V compound semiconductors.

He is a member of IEEE EDS.