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  1. (Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, Korea )
  2. (Smart Factory Multidisciplinary Program, Ewha Womans University, Seoul, Korea)



DLL, edge-detector, LiDAR sensor, T-latch, Vernier TDC

I. INTRODUCTION

Light detection and ranging (LiDAR) sensors have received a great deal of attention, especially for the applications of three-dimensional imaging systems such as unmanned autonomous vehicles. They can facilely detect the target’s location and recover three-dimensional (3-D) images. Typically, LiDAR sensors are based upon the time-of-flight (ToF) mechanism to measure the range between its optical source and targets located within the feasible detection range. They measure the time interval between the light-pulse emission and the reflected pulses from the targets with the speed of light, hence estimating the distance. The detection range may vary from a few mili-meters up to a few kilometers, depending upon their specific applications (1).

Fig. 1 illustrates the block diagram of a pulsed ToF-based LiDAR sensor, where the optical transmitter emits a focused optical pulse to a distant target. Simultaneously, the laser driver initializes the range measurements by sending a START pulse to the time-to-digital converter (TDC). Thereafter, the target reflects the transmitted optical pulse with a few percent reflection rate which is detected by the sensitive analog-front-end circuit. In particular, the optical receiver converts the optical signal into an electrical current via an input optical detector, i.e., a photodiode, and amplifies the incoming current to an output voltage through a transimpedance amplifier (TIA). Then, the TDC measures the time interval between the START pulse and the received STOP pulse, generating a corresponding digital output code. These pulsed ToF-based LiDAR sensors can detect targets precisely within its detection range, and therefore they can be applied for various fields such as the refinement of object recognition, navigation, collision avoidance, etc.

However, conventional LiDAR sensors can hardly identify the primary return pulse from the secondary pulses caused by multiple objects due to the nature of the reflected narrow pulses. Besides, timing accuracy can be severely deteriorated owing not only to the walk-error caused by the limited slew rates of the return pulses, but also to the slow response time of comparators. Therefore, several novel circuits have been introduced to compensate the notorious walk errors (2-5).

Fig. 1. Block diagram of a typical pulsed time-of-flight based LiDAR sensor.

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In (2), timing discrimination scheme by the differential voltage shift was exploited to mitigate the walk errors. The differential output voltages of TIA were split and shifted before being fed to comparators so that no external threshold voltage circuitry was needed. In (3), walk errors were compensated by the compensation curve representing the relationship between walk error and pulse length. This method not only compensated walk error successfully, but also achieved a wide dynamic range. However, these two methods needed complicated comparators and exploited two-channel TDCs for walk error compensation, thus leading to large chip area and power dissipation. In (4), a constant-delay detection method utilizing dual-threshold circuitry was introduced to enable the use of a single-channel TDC. Yet, it mandated careful design to achieve robustness against common-mode noises. In (5), high-precision TDCs were employed to obtain better detection of multiple targets in practice, thus resolving issues like echo, ambiguity, and walk error effectively. However, good linearity and high-resolution characteristics demanded additional intricate circuitry for high-precision measurements, which also raised design difficulties. In addition, the ring-type TDCs described in (5,6) degraded phase noise severely owing to the parallel-output-misalignment error that was caused by the delay mismatch of the loop counter and the arbiter set. Hence, we propose a novel 3-dimensional (3-D) modified Vernier TDC (MV-TDC) in this paper that can be exploited in a pulsed ToF-based LiDAR sensor to detect targets within the range between several centimeters to a few tens of meters.

Section II presents the architecture and operations of the proposed 3-D MV-TDC. Section III demonstrates the measured results. Then, conclusion is followed in Section IV.

II. Proposed 3-D Modified Vernier TDC

Fig. 2 illustrates the block diagram of the proposed three-dimensional modified Vernier TDC (3-D MV-TDC) that combines a 2-D modified Vernier TDC utilizing a resettable T-latch (RTL) as input circuitry as described in (7), and a delay-lock loop (DLL) preceded by an XOR gate (XOR) and an edge-detector with a few inverters. Here, the total time interval between the START and the STOP pulses can be represented by an 8-bit output digital code, i.e., a 4-bit coarse-control digital code and a 4-bit fine-control code. Both simulations and measurements confirm simultaneously that the maximum detection range of this proposed 3-D MV-TDC can reach 28.8 meters, which corresponds to 96-ns time interval with the resolution of 6 ns, i.e., (τ1-τ2) = 6 ns, and also that the minimum detection distance can be as short as 18.8 centi-meters that corresponds to 0.625-ns time interval.

1. 2-D Modified Vernier TDC

The proposed 2-D MV-TDC exploits a couple of RTLs followed by 15 comparators as arbiters. Basically, it shares the almost similar architecture to a conventional 2-D Vernier TDC. Therefore, the START pulse is delayed through arbiter chain with 18-ns delay in each arbiter, whereas the STOP pulse is delayed through arbiter chain with 12-ns delay in each arbiter, resulting in the timing resolution of 6 ns. Then, the arbiter chains generate a 15-bit output thermometer code that will be converted to a 4-bit binary digital data by using a Thermometer-to-Binary encoder.

Fig. 2. Block diagram of the proposed 3-D modified Vernier TDC.

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Fig. 3 depicts the simulated timing diagrams of the proposed 2-D MV-TDC with the RTL circuits that generate the T_START and T_STOP pulses, respectively.

The T_START signal is delayed by 18 ns (= τ1), while the T_STOP signal is delayed by 12 ns (= τ2) in each period. In this work, the longest delay is set to 126 ns for T_START and 36 ns for T_STOP.

The comparators (or arbiters) yield digital outputs from Q0 to Q14 with respect to the delayed position of the incoming input signal. As an example, (D, a) indicates the time position when the T_START and the T_STOP signals are overlapped. Then, the generated output thermometer codes are converted to 4-bit binary data.

Simulations confirm that the detection range of this 2-D MV-TDC reaches from 1.8 meters (corresponding to 6-ns time interval) up to 28.8 meters.

2. DLL with XOR & Edge-Detector

Fig. 2 also shows the block diagram of the DLL that is preceded by an XOR and a rising edge-detector (RED) with a few inverters. The combined XOR-RED gates generate a high-state pulse of which duration can be maintained only between each rising edge of the START and the STOP pulses. This high-state pulse is synchronized with the clock signal (CLK), and then the enable (EN) signal turns on the MOS transistors of each delay-cell in the delay lines. In short, these combined circuitry generates a high-state pulse starting from the rising edge of a START pulse and ending at the rising edge of a STOP pulse, during which the DLL operates to provide a 4-bit fine-control digital code with pico-second resolution.

The DLL core includes a control loop consisting of a phase detector (PD), a charge-pump (CP), a second-order loop-filter (LF), and delay-cells. This DLL topology is based upon the principle of constant propagation delay by utilizing the well-known matched series digital cells. Thereby, each delay-cell yields the output data from q0 to q14, of which delay is precisely trimmed by the ‘EN’ signal with pico-second resolution. Hence, the proposed DLL enables high-precision time interval measurements with reasonably low power consumption (5). Also, the total time interval can be estimated without the usage of a counter circuit, which is different from a conventional TDC that mandates a counter circuit to record the full reference clock periods between the START and the STOP pulses (8,9). Finally, a thermometer-to-binary converter is added to provide a 4-bit binary code.

Fig. 4 shows the simulated timing diagrams of the DLL fine-control loop, where the ‘EN’ signal is maintained from the rising edge of a START pulse up to that of a STOP pulse. The ‘EN’ signal turns on the MOS transistors of each delay cell to precisely trim the delay, and thus to generate 15-bit thermometer data. Finally, the 15-bit thermometer data are converted to 4-bit binary codes. Simulations confirm that the detection range of this proposed DLL with XOR-RED gates reaches from 18.8 centi-meters up to 3 meters (corresponding to 10-ns time interval).

III. Measurement Results

Fig. 3. Simulated timing diagrams of the 2-D modified Vernier TDC for coarse-control.

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Test chips of the proposed 3-D MV-TDC were implemented in a 0.13-μm CMOS technology.

Fig. 5 shows the test setup and the chip microphotograph, where the chip core occupies the area of 0.37 x 0.89 mm$^{2}$. DC measurements reveal that the 3-D MV-TDC chip dissipates 2.9 mW from a single 1.2-V supply. For range measurements, a waveform generator (Keysight, 33660A) was exploited to provide two pulses, i.e., the START and the STOP pulses with their phase shifted. Then, the parallel outputs of the 3-D MV-TDC were measured by using a logic analyzer (Saleae Logic Pro16).

Fig. 4. Simulated timing diagrams of the proposed DLL with an XOR and an edge-detector for fine-control.

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Fig. 5. Evaluation PB-board and its test setup for the proposed modified Vernier TDC with the chip microphotograph.

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Fig. 6 - 8 demonstrate the measured output digital codes of the 3-D MV-TDC for short-range, medium-range, and long-range targets, respectively. Fig. 6(a) shows the case with no time interval between the START and the STOP pulses, which corresponds to less than 18.8-cm distance to a target. Therefore, the coarse-control loop generates the output code of 0000, and also the fine-control loop provides 0000. Fig. 6(b) shows the measured results with 0.6-ns time interval between two pulses, which corresponds to 18.8-cm distance to a target. The coarse-control loop generates the output code of 0000, while the fine-control loop provides 0001.

Fig. 6. Measured results of the 3-D MV-TDC for short-range targets (a) with no time interval, (b) with 0.6 ns time interval between start and stop pulses.

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Fig. 7. Measured results of the 3-D MV-TDC for short-range targets (a) with 40-ns time interval, (b) with 60-ns time interval between start and stop pulses.

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Fig. 7 depicts the measured output digital codes for medium-range targets. Fig. 7(a) demonstrates the case of 40-ns time interval between the START and the STOP pulses, which corresponds to 12-meter distance to a target. The coarse-control loop generates the output code of 0110, while the fine-control loop provides 1111. Fig. 7(b) shows the measured results for 60-ns time interval, which corresponds to 18-meter distance to a target. The coarse-control loop generates the output code of 1001, while the fine-control loop provides 1111.

Fig. 8 demonstrates the measured output digital codes for long-range targets. With 90-ns time interval that corresponds to 27-meter distance to a target, the coarse-control loop generates the output code of 1110, while the fine-control loop provides 1111, as shown in Fig. 8(a). With 100-ns time interval corresponding to 30-meter distance, the coarse-control loop generates the output code of 1111, while the fine-control loop provides 1111, as shown in Fig. 8(b).

Fig. 8. Measured results of the 3-D MV-TDC for short-range targets (a) with 90-ns time interval, (b) with 40 ns time interval between start and stop pulses.

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Table 1. Performance Comparison with Prior Arts

PD: pseudo-diff delay-line, TA: time amplifier, GRO: gated ring oscillator, VR: Vernier ring, DPLL: digital phase-lock loop

* estimated from the time resolution multiplied by 2$^{\mathrm{N}}$ and the speed of light

∆FoM ${\equiv}$ power dissipation / (2$^{\mathrm{N}}$ * conversion rate * max. detection range)

Parameters

(10)

(11)

(12)

(13)

(14)

(15)

(16)

This Work

CMOS technology (nm)

90

90

130

130

65

130

130

130

Configuration

PD

TA

GRO

VR

2-D

3-D

3-D

3-D

Applications

DPLL

DPLL

DPLL

DPLL

DPLL

DPLL

ToF

LiDAR

Supply volage (V)

1.3

1.0

1.5

1.5

1.2

1.5

1.5

1.2

Number of bits (N)

5

9

11

12

7

8

11

8

Conversion rate (MS/s)

N/A

5

50

15

50

15

25

50

Detection range

*6 mm ~

19.2 cm

*0.4 mm ~19.2 cm

*1.8 mm ~

3.7 meter

*2.4 mm ~

9.83 meter

*1.4 mm ~

18.4 cm

*5 mm ~

1.27 meter

2.1 mm ~

4.3 meter

18.8 cm ~

28.8 meter

Power dissipation (mW)

6.9

3.0

2.2 ~ 21

7.5

1.7

4.5

0.33

2.9

Core area (mm2)

0.01

0.6

0.041

0.26

0.02

0.16

0.28

0.33

∆ FoM (fJ/step.meter)

N/A

12,207

5.8 ~ 55.4

12.4

1,443.6

922.7

37.5

7.9

Table 1 summarizes the performance of the proposed 3-D MV-TDC together with the previously reported prior arts. In (10), a pseudo-differential delay line architecture was utilized. However, it dissipated a large power of 6.9 mW from a 1.3-V supply and the detection range was limited to 19.2 cm only. In (11), a time amplifier was exploited to achieve 9-bit output codes. Yet, the detection range was still limited to 19.2 cm only. In (12), a gated ring oscillator configuration was introduced. Yet, it required a 1.5-V supply, thus resulting in rather large power consumption with the detection range up to 3.7 meters. In (13), the Vernier ring configuration was presented. It consumed a large power of 7.5 mW, even though the detection range was extended to 9.83 meters. Lower power dissipation and smaller chip area were demonstrated in (14). Still, the detection range was significantly limited to 18 centi-meters. Recently, a 3-D Vernier TDC was demonstrated in (15) with the detection range from 5 centi-meters up to 1.27 meters. But, it consumed a comparatively large power of 4.5 mW. Another 3-D Vernier TDC with very low power dissipation was introduced in (16). However, its detection range was limited to 4.3 meters only. For comparison purposes, we utilize a figure-of-merit (FoM) that is defined as the ratio of power dissipation by the three multiplied factors (i.e., the maximum detection range, the conversion rate, and 2$^{\mathrm{N}}$), where the number of bits (N) is utilized to facilitate the performance comparison, instead of the effective value (N$_{\mathrm{eff}}$).

Hence, it can be concluded that the proposed 3-D MV-TDC provides a potential to realize a low-power low-cost solution with comparatively long-range detection capability, which is particularly suitable for the applications of LiDAR sensors.

IV. CONCLUSIONS

We have realized a 3-D modified Vernier TDC in 0.13-μm CMOS for LiDAR sensor applications, where the 2-D MV-TDC shows the resolution of 6 ns for detecting the distance from 1.8 meters up to 28.8 meters, whereas the DLL preceded by an XOR and an edge-detector provides the resolution of 0.625 ns to detect the distance from 18.8 centimeters up to 3 meters. It can be concluded that the proposed 3-D MV-TDC provides a low-power long-range solution for LiDAR sensors.

ACKNOWLEDGMENTS

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2020R1A2C1008879). The EDA tool was supported by the IC Design Education Center. The support of BrainKorea 12-four is acknowledged.

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Author

Ying He
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received the B.S. degree in Telecommunications Engineering from Yanbian University of Science & Technology, Yanji, China, in 2012. She is currently working toward the Ph.D. degree in the analog circuits and systems Lab. at Ewha Womans University. Her current research interests include integrated circuits and architectures for high-speed CMOS analog front-end designs for optical communication systems.

Ji-Eun Joo
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received the B.S. degree in electronic and electrical engi-neering from Ewha Womans University, Korea, in 2020. She is currently working toward the MSc degree in the analog circuits and systems lab. at the same university. Her current research interests include silicon photonics, and CMOS optoelectronic integrated circuits and architectures for short distance optical application systems and sensor interface IC designs.

Sung Min Park
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received the B.S. degree in electrical and electronic engineering from KAIST, Korea, in 1993. He received the M.S. degree in electrical engineering from Univer-sity College London, U.K., in 1994, and the Ph.D. degree in electrical and electronic engineering from Imperial College London, U.K., in May 2000. In 2004, he joined the faculty of the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea, where he is currently a Professor. His research interests include high-speed analog/digital integrated circuit designs for the applications of optical interconnects, silicon photonics, and RF communications. Prof. Park has served on the technical program committees of a number of international conferences including ISSCC (2004-2009).