This paper presents low-power low-noise 24-GHz CMOS LNA (low noise amplifier) for automotive collision avoidance radar. The proposed circuit is fabricated using 65 nm RF CMOS technology, and it is powered by 1.2 V supply. To increase voltage gain and decrease power consumption, this circuit has cascode scheme, and it is optimized to decrease noise figure. Cascode inductive source degeneration technique is also utilized to match the circuit to source impedance. The proposed LNA showed the lowest power consumption of 4.59 mW and the lowest noise figure of 2.98 dB with high voltage gain of 24.3 dB as compared to recently published results. It also showed the smallest chip area of 0.6×0.6 mm$^{2}$, and the size of the core cell of 0.31×0.35 mm$^{2}$ without pads as compared to recently reported results. We expect that the proposed LNA is suitable for GHz-band automotive collision avoidance radar.

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## I. INTRODUCTION

The rapid growth of wireless communications has pursued on low power, low cost, and
high performance receivers. In most cases, the millimeter wave circuits were considered
by utilizing CMOS technology. The main wireless receiver task is to detect the desired
modulated signals. Wireless receivers have to perform several functions such as tuning
to the wanted signal carriers, filtering out the undesired signals, and amplifying
the desired signal to compensate for power losses occurring during transmission ^{(1}^{-7)}.

Thanks to growing speed of radar-based collision avoidance systems, vehicles can see
the other objects including pedestrian and other vehicles, anticipate accidents and
collision, control the braking system and steering wheel to save the people life,
and reduce the severity of collisions. Radar transceivers are installed on the vehicles
which operate in the all types of weather or sometimes both laser and camera are utilized
to anticipate the imminent collision on the street or highways. At first, collision
avoidance systems search the surrounded area of the vehicles to detect the imminent
crash. When the detection process is done, the system warns to the drivers by light,
vibration in steering wheel or seat belt, and then the system based on the predefined
distance fastens the seat belt and brakes, and finally controls the steering wheel
to save the driver. The main frequency bands of radar applications are 24 GHz and
77~GHz. For the sake of detection of other near vehicles in the medium-short range
and wide beam, 24 GHz is mainstream. The receiver for the automotive radar system
operates in the band of 24 GHz frequency which is composed of LNA (low noise amplifier),
down-conversion mixer, and VCO (voltage-controlled oscillator). The LNA is a crucial
component for radio receivers, and it must meet several requirements such as good
input matching, adequate gain and reasonably low noise ﬁgure to elevate received signal-to-noise
ratio as well as energy-efficiency for battery-powered portable devices ^{(7}^{-9)}.

This paper presents low-power low-noise 24-GHz CMOS LNA for automotive collision avoidance radar. The proposed circuit is fabricated using 65 nm RF CMOS technology and it is powered by 1.2 V supply. To increase voltage gain, this circuit has cascode scheme, and it is optimized to decrease noise figure. Cascode inductive source degeneration technique is also utilized to match the circuit to source impedance.

## II. CIRCUIT DESIGN AND ANALYSIS

### 2.1 Overview of 24 GHz Radar

The automotive radar is the most promising and robust solution to vehicle sensing
requirements in terms of environmental conditions, measurement capabilities, and ease
of installation. The best frequency for this radar depends on the targeted application.
In fact, this choice of frequency involves trade-off between several factors such
as transmitted and received powers. Fig. 1 shows a simple ACC (adaptive cruise control) system. The systems consist of three
types such as short range radar (SRR), medium-short range (MRR) and long range radar
(LRR). The CMOS-based 24-GHz SRR sensors with distance up to approximately 30 meters
are under development for a variety of further applications. The SRR may cover many
applications such as parking aid, ACC with stop and go, pre-crash or collision warning,
back-up function, etc. Since it has also better performance in azimuth angle and in
range measurements, it is suitable for automotive applications providing parking aid,
pre-crash detection, side object detection and blind spot detection ^{(1}^{-6)}.

### 2.2 Design of the proposed 24 GHz CMOS LNA

Fig. 2 shows the proposed low-power low noise-noise 24-GHz CMOS LNA. This LNA is implemented using the 65 nm RF CMOS process. This process has been retained because of its good low noise performance, the unity current gain cut-off frequency ($f_{T}$) of 120 GHz and the maximum oscillation frequency ($f_{max}$) of 140 GHz. Successful integration of the LNA at 24 GHz depends on minimizing parasitic capacitances and losses to maintain adequate gain, designing with low voltage swing for low breakdown devices, and achieving sufficient linearity required for low spectrally efficient and variable envelope modulation scheme.

Providing a resistive input impedance of 50 Ω is one critical requirement of an LNA.
The 50 Ω termination is required mainly by the previously band select filter $L_{3}$
with parasitic capacitance and transistor $M_{1}$ is biased by adding parasitic capacitance
to the input impedance matching. The third-order non-linear transconductance coefficient
$g_{m3}$ is performed by gate-drain and gate-source capacitances of basic components,
and it reduces linearity performance. To improve noise figure and linearity, we propose
a CG (common gate) NMOS-PMOS inverter scheme for the cascode LNA as a linearizer.
The proposed linearization method accepts NMOS and PMOS transistors into common gate
configuration with the second-order and third-order nonlinearity to improve the linearity
performance ^{(9,}^{10)}.

To reach very low third-order distortion and low power, it is very important to reduce the second-order and third-order nonlinearities. It is very important to minimize or cancel $g_{m2}$ and $g_{m3}$ to decrease the third-order intermodulation distortion and to improve IIP3 (third-order input intercept point). The inductor $L_{2}$, and the parasitic capacitances at the drain of $M_{2}$ and $M_{4}$ form provide broadband network.

Let’s consider drain current $I_{d_{total}}$ of $M_{1}$ through the $M_{2}$ and $M_{3}$ transistors as shown in Fig. 3. For $M_{4}$, $V_{g4}$ = $V_{dd}$, $V_{s4}$ = $V_{d3}$, $I_{d4}$ = ($V_{dd}$-$V_{d4}$)/$R_{out}$, $I_{d4}$ = $I_{d3}$ and $I_{d4}$ = 0, since $M_{1}$ is connected to the ground through capacitor $C_{1}$ for $d_{1}$ = 0. From KCL, $I_{s3}$ = $d_{1}$ + $I_{s2}$, $I_{s2}$ = $I_{s3}$, $V_{dd}$-$I_{d4}$$R_{out}$-$V_{ds4}$-$V_{ds3}$ = $V_{ds2}$, and $V_{dd}$ = $I_{d4}$$R_{out}$ + $V_{d4}$, and we obtain Eqs. (1)-(3).

##### (2)

$$I_{d 3}=g_{m 1_{3}} (-V_{g s_{3}})+g_{m 2_{3}} (-V_{g s_{3}})^{2}+g_{m 2_{3}} (-V_{g s_{3}})^{3}$$

##### (3)

$$\begin{aligned} I_{d_{\text {total }}}\left(V_{1}\right)=& I_{d 2}+I_{d 3}=\left(g_{m 1_{2}} V_{g s_{2}}+g_{m 2_{2}} V_{g s_{2}}^{2}+g_{m 3_{2}} V_{g s_{2}}^{3}\right) \\ &+g_{m 1_{3}}\left(-V_{g s_{3}}\right)+g_{m 2_{3}}\left(-V_{g s_{3}}\right)^{2}+g_{m 2_{3}}\left(-V_{g s_{3}}\right)^{3} \end{aligned}$$Since $V_{gs3}$ is a function of $V_{gs2}$, it is expressed to power series of $V_{gs2}$ as expressed by Eq. (4).

where $C_{i}S$ are generally frequency dependent. In practice, the π-network cancels
the effects of $c_{2}$ and $c_{3}$ at the frequency of interest. To find the coefficient
$C_{i}S$, we should solve the equation after expanding $I_{d_{total}}$ as a power
series of $V_{gs2}$ and replacing it with Eq. (4), and then we obtain Eq. (5) ^{(4)}.

##### (5)

$$\begin{aligned} I_{d_{total}} &=I_{d 3}+I_{d 2} \\ & \cong\left(g_{m 1_{3}}+c_{1} g_{m 1_{2}}\right) V_{b 3}+\left(g_{m 2_{3}}+c_{1}^{2} g_{m 2_{2}}\right) V_{b 3}^{2}+\left(g_{m 3_{3}}+c_{1}^{3} g_{m 3_{2}}\right) V_{b 3}^{3} \end{aligned}$$
where $g_{m1}$, $g_{m2}$ and $g_{m3}$ are the main transconductance, second-order
and third-order nonlinearity coefficients, respectively ^{(4)}. The second order nonlinearity is canceled in output due to cut off phase signal
by NMOS and PMOS. The optimum biasing is used to obtain a high IIP3 by reducing the
total $g_{m3}$, and the IIP3 can be calculated by Eq. (6) ^{(8)}.

The $g_{m3,d3}$ changes from positive to negative when the transistor moves from weak to strong inversion region. In other words, by changing gate bias voltage of PMOS transistor, the parameter $C_{1}$ can be varied. It can be deduced from Eq. (4).

### 2.3 Small Signal Analysis

Fig. 4 shows simplified high-frequency small signal model of cascade topology with inductively degenerated scheme for the LNA. By applying the KCL at source node, we obtain Eq. (7).

where W and L represent the transistor’s width and length, respectively, and $C_{ox}$ is gate capacitance per unit area.

By applying the KCL at drain node $d_{1}$ of $M_{1}$, we get Eqs. (8)-(13).

##### (8)

$$\left(V_{d 1}-V_{g 1}\right) j w C_{g d 1}+g_{m 1} V_{g s 1}+\frac{\left(V_{d 1}-V_{s 1}\right)}{r_{0}}+\frac{\left(V_{d 1}-V_{s 2}\right)}{j w L_{3}}=0$$

##### (9)

$$\left(V_{d 1}-V_{g 1}\right) j w C_{g d 1}+g_{m 1} V_{g s 1}+\frac{V_{d s1}}{r_{0}}+\frac{\left(V_{d 1}-V_{s 2}\right)}{j w L_{3}}=0$$

##### (10)

$$\begin{array}{l} \left(V_{d 1}-V_{g 1}\right)\left(-\mathrm{w}^{2} L_{3} C_{g d 1}\right) r_{0}+j w L_{3} r_{0} g_{m 1} V_{g s 1}+j w L_{3} V_{d s 1} \\ +r_{0}\left(V_{d 1}-V_{s 2}\right)=0 \end{array}$$

##### (11)

$$\begin{array}{l} V_{d 1}\left[-w^{2} L_{3} r_{0} C_{g d 1}+r_{0}\right]+V_{g 1} w^{2} L_{3} r_{0} C_{g d 1}-r_{0} V_{s 2} \\ +j w L_{3} V_{d s 1}+j w L_{3} r_{0} g_{m 1} V_{g s 1}=0 \end{array}$$

##### (12)

$$\begin{array}{l} V_{d 1}\left[-w^{2} L_{3} r_{0} C_{g d 1}+r_{0}\right]+V_{g 1} w^{2} L_{3} r_{0} C_{g d 1}-r_{0} V_{s 2}+j w L_{3} V_{d 1} \\ -j w L_{3} V_{s 1}+j w L_{3} r_{0} g_{m 1} V_{g 1}-j w L_{3} r_{0} g_{m 1} V_{s 1}=0 \end{array}$$

##### (13)

$$\begin{aligned} &V_{d 1}\left[-w^{2} L_{3} r_{0} C_{g d 1}+r_{0}+j w L_{3}\right]+V_{g 1}\left[w^{2} L_{3} r_{0} C_{g d 1}+\right.\\ &\left.j w L_{3} r_{0} g_{m 1}\right]+V_{s 1}\left[-j w L_{3}-j w L_{3} r_{0} g_{m 1}\right]-r_{0} V_{s 2}=0 \end{aligned}$$

Now let’s analyze the input impedance of the cascade topology using inductive source degeneration technique. The transistor $M_{1}$ is replaced by a high-frequency small-signal model consisting of gate-source capacitor $C_{gs1}$, gate-drain capacitor $C_{gd1}$, $g_{m1}$ and source degeneration inductor $L_{1}$. By applying the KCL at source node $s_{1}$, we also obtain Eqs. (14)-(16).

##### (14)

$$I_{i n}=\frac{V_{s 1}}{R_{i n}}+\frac{V_{s 1}}{j w L_{1}}-g_{m 1} V_{g s 1}-\frac{V_{d s 1}}{r_{0}}-V_{d s 1} j w\left(\frac{c_{g d 1} c_{g s 1}}{c_{g d 1}+c_{g s 1}}\right)$$

##### (15)

$$I_{i n}=V_{s 1}\left(\frac{1}{R_{i n}}+\frac{1}{j w L_{1}}\right)-g_{m 1} V_{g s 1}-V_{d s 1} \frac{1}{r_{0}}+j w\left(\frac{c_{g d 1} c_{g s 1}}{c_{g d 1}+c_{g s 1}}\right)$$

##### (16)

$$\begin{aligned} I_{i n}=& V_{s 1}\left[\frac{1}{R_{i n}}+\frac{1}{j w L_{1}}+g_{m 1}+\frac{1}{r_{o}}+j w\left(\frac{C_{g d 1} C_{g s 1}}{C_{g d 1}+C_{g s 1}}\right)\right] \\ &-g_{m 1} V_{g 1}-V_{d 1}\left[\frac{1}{r_{0}}+j w\left(\frac{c_{g d 1} c_{g s 1}}{c_{g d 1}+c_{g s 1}}\right)\right] \end{aligned}$$For AC analysis, $C_{in}$ can be shorted, and by neglecting the term $V_{d1}$ and $V_{g1}$, and using Eqs. (14) and (15), we obtain Eqs. (17) and (18). $V_{in}$=$V_{s1}$ by inserting this value and rearranging, so the input impedance $Z_{in}$ is expressed by Eq. (19).

##### (17)

$$I_{i n}=V_{i n}\left[\frac{1}{R_{i n}}+\frac{1}{j w L_{1}}+g_{m 1}+\frac{1}{r_{o}}+j w\left(\frac{c_{g d 1} c_{g s 1}}{c_{g d_{1}}+c_{g s 1}}\right)\right]$$

##### (19)

$$Z_{i n}=\frac{1}{\left[\frac{1}{R_{i n}}+\frac{1}{j w L_{1}}+g_{m 1}+\frac{1}{r_{0}}+j w\left(\frac{c_{g d_{1}} c_{g s 1}}{\left.c_{g d 1}+c_{g s 1}\right)}\right)\right]}$$where $Z_{in}$ and output impedance $Z_{out}$ of each stage are optimized at 24 GHz, and we can simplify Eq. (19) into Eq. (20).

where $X_{L1}$ and $X_{C}=\frac{1}{j w\left(\frac{c_{g d_{1}} c_{g s 1}}{c_{g d_{1}}+c_{g s 1}}\right)}$

By assuming $r_{0}=∞$, we get the simplified form of $Z_{in}$as shown below.

On deactivating the input source $V_{in}$ and applying KCL at the output node, we can get output impedance $Z_{out}$. At the input node $s_{1}$, we also obtain Eqs. (22) and (23).

##### (22)

$$I_{s 1}=g_{m 1} V_{g s 1}+\frac{V_{d s 1}}{r_{0}}+V_{d s 1} j w\left(\frac{c_{g d_{1}} c_{g s 1}}{c_{g d 1}+c_{g s 1}}\right)$$

By applying KCL at the output node $d_{4}$, inserting $V_{d4}$=$V_{out}$, and rearranging, we get Eqs. (24)-(26).

##### (24)

$$\frac{V_{\text {out }}-V_{s 4}}{r_{0}}+g_{m 4} V_{g s 4}+\left[\left(\frac{R_{\text {out }}+j w L_{\text {out }} \frac{1}{j w C_{\text {gd4 }}}}{R_{\text {out }}+j w L_{\text {out }}+\frac{1}{j w C_{\text {gd4 }}}}\right)+\frac{1}{j w C_{g s t}}\right]\left(V_{\text {out }}-V_{s 4}\right)$$

##### (25)

$$\frac{V_{o u t}}{r_{o}}+V_{o u t}\left[\left(\frac{R_{o u t}+j w L_{o u t} \frac{1}{j w c_{g d 4}}}{R_{o u t}+j w L_{o u t}+\frac{1}{j w C_{g d 4}}}\right)+\frac{1}{j w c_{g s 4}}\right]=I_{o u t}$$

##### (26)

$$Z_{\text {out}}=\left[\frac{1}{r_{o}}+\frac{R_{\text {out}}+j w L_{\text {out}}}{j w C_{\text {gd4}}\left(R_{\text {out}}+j w L_{\text {out}}\right)+1}+\frac{1}{j w c_{g s 4}}\right]^{-1}$$

##### (27)

$$Z_{\text {out}}=\left[\frac{1}{r_{0}}+\frac{1}{j w C_{g d 4}+G_{\text {out}}}+\frac{1}{j w C_{g s 4}}\right]^{-1}$$where $G_{\text {out}}=\frac{1}{R_{\text {out}}+j w L_{\text {out}}}$, by assuming $r_{0}=∞$, we obtained the simplified form of $Z_{out}$ as shown in Eq. (28).

##### (28)

$$Z_{\text {out}}=\frac{j w c_{g s 4}\left(j w c_{g d 4}+G_{o u t}\right)}{j w\left(c_{g d 4}+c_{g s 4}\right)+G_{o u t}}$$Now let’s get voltage gain. From the voltage and current of transistors $M_{1}$, $M_{2}$, $M_{3}$ and $M_{4}$, we also obtain Eqs. (29)-(35).

By rearranging Eqs. (29) and (35), we get Eqs. (36)-(38).

The voltage gain of the LNA should be much larger to reduce the noise figure. From high-frequency small signal model as shown in Fig. 4, we also obtain Eqs. (39)-(41).

If we assume that $r_{o1}=r_{o2}=r_{o3}=r_{o4}=r_{o}$, voltage gain is expressed by Eq. (42).

By assuming $r_{0}=∞$, therefore we get Eq. (43).

##### (43)

$$A_{v}=g_{m 1} g_{m 3} g_{m 4}\left(R_{o u t}+j w L_{o u t}\right) \lim _{r_{0-\infty}}\left(\frac{j w L_{3} r_{0}}{2 j w L_{3}+r_{0}}\right) \lim _{r_{0-\infty}}\left(\frac{r_{0}}{2+r_{0} g_{m 4}}\right)$$Eq. (43) is also simplified as described in Eqs. (44) and (45).

##### (44)

$$A_{v}=g_{m 1} g_{m 3} g_{m 4}\left(R_{o u t}+j w L_{o u t}\right) \left(\frac{jwL_{3}}{g_{m 4}}\right)$$

where $X_{Lout}$= $j_{ω}L_{out}$, $X_{L3}$ = $j_{ω}L_{3}$ and $G_{T}$ = $g_{ml}g_{m3}$.

The noise figure ($NF$) in LNA determines the inherent LNA noise added to the desired
or wanted signal during the process of amplification. $NF$ is a function of source
admittance looking into the input terminal of the two-port network. To achieve the
$NF_{min}$, an optimum source admittance that results in minimum noise figure, namely
$Y_{opt}$, should be introduced to the network. The expressions for $NF_{min}$ and
$Y_{opt}$ can be derived for a MOS device by considering a two-port network model
for the MOS device. In this model the gate-source terminal is the input port, and
the drain-source terminal is the output port. When source admittance presented to
transistor ($Y_{s}$) is matched at $Y_{opt}$, the NF has almost $NF_{min}$ ^{(11,}^{12)}.

### 2.4 Layout Issues

The circuits are designed and fabricated using 65 nm RF CMOS technology. This technology
offers six metal layers with two top layers of 0.6$\mu \mathrm{m}$ thick copper. Shield
pads for inductors are employed at each port. Fig. 5 shows die photograph of the proposed LNA. Grounded metal underneath the pads prevents
loss of the signal power and noise generation associated with the substrate resistance.
Ground rings are placed around each transistor at minimum distance to reduce the substrate
loss. To minimize parasitic capacitance all transistors are designed by folded structure
^{(9)}. Signal lines were wide enough to meet electro-migration requirements. Ground lines
were made wide to provide low impedance paths. The decoupling capacitor was added
to bypass high frequency noise from the bias voltage. Grounded guard ring with substrate
connection surrounds the inductor to minimize substrate noise. The MIM capacitors
are used for high quality factors and the resistors of tantalum nitride thin film
are used. Large on-chip bypass capacitors are placed between each $V_{DD}$and ground.
The die occupies 0.60${\times}$0.60 mm$^{2}$ including pads and 0.31${\times}$0.35
mm$^{2}$ without pads.

## III. RESULTS AND DISCUSSIONS

The input and output pads are laid out in GSG configuration with a pitch of 50$\mu \mathrm{m}$ to perform wafer level testing for LNA using a probe station with network analyzer. We performed 2-port measurements. The measurements are based on a separate LNA test chip. The power of ${-}$20 dBm is applied from the synthesized sources at both port 1 and port 2. We applied the attenuators of 0 dB at both port1 and port2.

Obviously, downscaling of CMOS technologies has significant impact on the design of
analog and radio frequency circuits. Particularly, in low supply voltage circuits,
as the technology downscales, the available voltage headroom decreases, and so it
makes the design procedure difficult. Additionally, since the voltage headroom is
smaller, the low power consumption in wireless and electronic portable devices and
applications is becoming more important. In analog and RF blocks, high output power
with high efficiency is desirable, but with the above-mentioned limitations on the
recent technologies, achieving these goals requires special attention on the designing
circuits with new techniques and topologies. From Fig. 2 and 3, the proposed LNA showed total dc current of 3.825 mA at 1.2 V supply, so we
obtained the lowest power consumption of 4.59 mW as compared to conventional results
^{(13-}^{17)}.

Fig. 6 shows (a) input and output return losses (S$_{11}$, S$_{22}$), and (b) reverse isolation
(S$_{12}$). Input and output impedance matching is so important to obtain low input
and output return losses. Ideal input and output impedances of the amplifier must
have 45${\sim}$50 Ω at the operation frequency. As shown in Fig. 6, the LNA showed very low input return loss of -32.8 dB, very low output return loss
of -32.7 dB, and very low reverse isolation of -47 dB as compared to conventional
results ^{(13-}^{17)}.

Voltage gain is very important parameter in GHz-band LNA. Fig. 7 shows voltage gain ($A_{v}$). From the proposed circuit, ${\Gamma}$$_{L}$ = ${\Gamma}$$_{in}$
${\approx}$ 0, so it has value of $A_{v}$${\approx}$ S$_{21}$ ^{(11,}^{12)}. As shown in Fig. 7, the proposed LNA showed very high voltage gain of 24.3 dB at the operation frequency
of 24~GHz as compared to conventional results ^{(13-}^{16)}.

Fig. 8 shows noise figure. Noise figure is measurement factor of degradation of signal-to-noise
ratio (SNR) as the incoming signal from antenna traverses the receiver frontend. Mathematically,
noise figure is defined as the ratio of the input SNR to the output SNR of the system.
To reduce noise figure, $Y_{s}$ is matched at $Y_{opt}$ in the proposed amplifier.
As shown in Fig. 8, the proposed LNA showed very low noise figure of 2.98 dB as compared to conventional
results ^{(13-}^{17)}.

To verify performance of the proposed LNA, we carried out simulations using ADS and layout using Cadence, and calculation is extracted using high-frequency small signal equivalent model.

Table 1. Comparison summary for recently reported research results

The performance summary of the proposed LNA is compared in Table 1. As can be seen from Table 1, the proposed LNA showed the lowest power consumption of 4.59 mW, the highest voltage
gain of 24.3 dB, and the lowest noise figure of 2.98 dB as compared to conventional
results ^{(13-}^{16)}. It also has the smallest die size 0.31${\times}$0.35 mm$^{2}$ without pads as compared
to recently reported research results ^{(13-}^{16)}.

## IV. CONCLUSIONS

In this paper, we proposed low-power low-noise 24-GHz CMOS LNA for automotive collision avoidance radar. This circuit is implemented in 65 nm RF CMOS process. To increase voltage gain and decrease power consumption, we utilized cascode inductive source degeneration technique. The LNA was optimized by minimization of the inherent LNA noise added to the desired or wanted signal during the process of amplification to reduce noise figure. The proposed LNA showed total dc current of 3.825 mA at 1.2 V supply, so we obtained the lowest power consumption of 4.59 mW as compared to conventional results. It also showed the lowest noise figure of 2.98 dB, high voltage gain of 24.3~dB, good S-parameter results and small die size 0.31${\times}$0.35 mm$^{2}$ without pads as compared to recently reported research results.

### ACKNOWLEDGMENTS

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2018R1D1A1B07043286).

### REFERENCES

## Author

Murod Kurbanov, received the BS in electronics engineering from Tashkent University of Information Technologies, Tashkent, Uzbekistan, in 2012, and the MS degree in information and communication engineering from Pukyong National University, Busan Korea, in 2017.

He is currently taking the PhD degree in information and communications engineering from Pukyong National University.

His current research interests include the design and testing of RF integrated circuits and the design and testing of System-on-Chip.

Jee-Youl Ryu, received the BS and MS degrees in electronics engi-neering from Pukyong National University, Busan, Korea, in 1993 and 1997, respectively, and the PhD degree in electrical engineering from Arizona State University, Tempe, in December 2004.

He is currently a professor at Pukyong National University.

His current research interests include the design and testing of System-on-Chip, the design and testing of RF integrated circuits, and the design of embedded system.