2.1 Overview of 24 GHz Radar

The automotive radar is the most promising and robust solution to vehicle sensing requirements in terms of environmental conditions, measurement capabilities, and ease of installation. The best frequency for this radar depends on the targeted application. In fact, this choice of frequency involves trade-off between several factors such as transmitted and received powers. Fig. 1 shows a simple ACC (adaptive cruise control) system. The systems consist of three types such as short range radar (SRR), medium-short range (MRR) and long range radar (LRR). The CMOS-based 24-GHz SRR sensors with distance up to approximately 30 meters are under development for a variety of further applications. The SRR may cover many applications such as parking aid, ACC with stop and go, pre-crash or collision warning, back-up function, etc. Since it has also better performance in azimuth angle and in range measurements, it is suitable for automotive applications providing parking aid, pre-crash detection, side object detection and blind spot detection ^(1-6).

2.2 Design of the proposed 24 GHz CMOS LNA

Fig. 2 shows the proposed low-power low noise-noise 24-GHz CMOS LNA. This LNA is implemented using the 65 nm RF CMOS process. This process has been retained because of its good low noise performance, the unity current gain cut-off frequency ($f_{T}$) of 120 GHz and the maximum oscillation frequency ($f_{max}$) of 140 GHz. Successful integration of the LNA at 24 GHz depends on minimizing parasitic capacitances and losses to maintain adequate gain, designing with low voltage swing for low breakdown devices, and achieving sufficient linearity required for low spectrally efficient and variable envelope modulation scheme.

Providing a resistive input impedance of 50 Ω is one critical requirement of an LNA. The 50 Ω termination is required mainly by the previously band select filter $L_{3}$ with parasitic capacitance and transistor $M_{1}$ is biased by adding parasitic capacitance to the input impedance matching. The third-order non-linear transconductance coefficient $g_{m3}$ is performed by gate-drain and gate-source capacitances of basic components, and it reduces linearity performance. To improve noise figure and linearity, we propose a CG (common gate) NMOS-PMOS inverter scheme for the cascode LNA as a linearizer. The proposed linearization method accepts NMOS and PMOS transistors into common gate configuration with the second-order and third-order nonlinearity to improve the linearity performance ^(9,10).

To reach very low third-order distortion and low power, it is very important to reduce the second-order and third-order nonlinearities. It is very important to minimize or cancel $g_{m2}$ and $g_{m3}$ to decrease the third-order intermodulation distortion and to improve IIP3 (third-order input intercept point). The inductor $L_{2}$, and the parasitic capacitances at the drain of $M_{2}$ and $M_{4}$ form provide broadband network.

Let’s consider drain current $I_{d_{total}}$ of $M_{1}$ through the $M_{2}$ and $M_{3}$ transistors as shown in Fig. 3. For $M_{4}$, $V_{g4}$ = $V_{dd}$, $V_{s4}$ = $V_{d3}$, $I_{d4}$ = ($V_{dd}$-$V_{d4}$)/$R_{out}$, $I_{d4}$ = $I_{d3}$ and $I_{d4}$ = 0, since $M_{1}$ is connected to the ground through capacitor $C_{1}$ for $d_{1}$ = 0. From KCL, $I_{s3}$ = $d_{1}$ + $I_{s2}$, $I_{s2}$ = $I_{s3}$, $V_{dd}$-$I_{d4}$$R_{out}$-$V_{ds4}$-$V_{ds3}$ = $V_{ds2}$, and $V_{dd}$ = $I_{d4}$$R_{out}$ + $V_{d4}$, and we obtain Eqs. (1)-(3).

Since $V_{gs3}$ is a function of $V_{gs2}$, it is expressed to power series of $V_{gs2}$ as expressed by Eq. (4).

where $C_{i}S$ are generally frequency dependent. In practice, the π-network cancels the effects of $c_{2}$ and $c_{3}$ at the frequency of interest. To find the coefficient $C_{i}S$, we should solve the equation after expanding $I_{d_{total}}$ as a power series of $V_{gs2}$ and replacing it with Eq. (4), and then we obtain Eq. (5) ⁽⁴⁾.

where $g_{m1}$, $g_{m2}$ and $g_{m3}$ are the main transconductance, second-order and third-order nonlinearity coefficients, respectively ⁽⁴⁾. The second order nonlinearity is canceled in output due to cut off phase signal by NMOS and PMOS. The optimum biasing is used to obtain a high IIP3 by reducing the total $g_{m3}$, and the IIP3 can be calculated by Eq. (6) ⁽⁸⁾.

The $g_{m3,d3}$ changes from positive to negative when the transistor moves from weak to strong inversion region. In other words, by changing gate bias voltage of PMOS transistor, the parameter $C_{1}$ can be varied. It can be deduced from Eq. (4).

2.3 Small Signal Analysis

Fig. 4 shows simplified high-frequency small signal model of cascade topology with inductively degenerated scheme for the LNA. By applying the KCL at source node, we obtain Eq. (7).

where W and L represent the transistor’s width and length, respectively, and $C_{ox}$ is gate capacitance per unit area.

By applying the KCL at drain node $d_{1}$ of $M_{1}$, we get Eqs. (8)-(13).

Now let’s analyze the input impedance of the cascade topology using inductive source degeneration technique. The transistor $M_{1}$ is replaced by a high-frequency small-signal model consisting of gate-source capacitor $C_{gs1}$, gate-drain capacitor $C_{gd1}$, $g_{m1}$ and source degeneration inductor $L_{1}$. By applying the KCL at source node $s_{1}$, we also obtain Eqs. (14)-(16).

For AC analysis, $C_{in}$ can be shorted, and by neglecting the term $V_{d1}$ and $V_{g1}$, and using Eqs. (14) and (15), we obtain Eqs. (17) and (18). $V_{in}$=$V_{s1}$ by inserting this value and rearranging, so the input impedance $Z_{in}$ is expressed by Eq. (19).

where $Z_{in}$ and output impedance $Z_{out}$ of each stage are optimized at 24 GHz, and we can simplify Eq. (19) into Eq. (20).

where $X_{L1}$ and $X_{C}=\frac{1}{j w\left(\frac{c_{g d_{1}} c_{g s 1}}{c_{g d_{1}}+c_{g s 1}}\right)}$

By assuming $r_{0}=∞$, we get the simplified form of $Z_{in}$as shown below.

On deactivating the input source $V_{in}$ and applying KCL at the output node, we can get output impedance $Z_{out}$. At the input node $s_{1}$, we also obtain Eqs. (22) and (23).

By applying KCL at the output node $d_{4}$, inserting $V_{d4}$=$V_{out}$, and rearranging, we get Eqs. (24)-(26).

where $G_{\text {out}}=\frac{1}{R_{\text {out}}+j w L_{\text {out}}}$, by assuming $r_{0}=∞$, we obtained the simplified form of $Z_{out}$ as shown in Eq. (28).

Now let’s get voltage gain. From the voltage and current of transistors $M_{1}$, $M_{2}$, $M_{3}$ and $M_{4}$, we also obtain Eqs. (29)-(35).

By rearranging Eqs. (29) and (35), we get Eqs. (36)-(38).

The voltage gain of the LNA should be much larger to reduce the noise figure. From high-frequency small signal model as shown in Fig. 4, we also obtain Eqs. (39)-(41).

If we assume that $r_{o1}=r_{o2}=r_{o3}=r_{o4}=r_{o}$, voltage gain is expressed by Eq. (42).

By assuming $r_{0}=∞$, therefore we get Eq. (43).

Eq. (43) is also simplified as described in Eqs. (44) and (45).

where $X_{Lout}$= $j_{ω}L_{out}$, $X_{L3}$ = $j_{ω}L_{3}$ and $G_{T}$ = $g_{ml}g_{m3}$.

The noise figure ($NF$) in LNA determines the inherent LNA noise added to the desired or wanted signal during the process of amplification. $NF$ is a function of source admittance looking into the input terminal of the two-port network. To achieve the $NF_{min}$, an optimum source admittance that results in minimum noise figure, namely $Y_{opt}$, should be introduced to the network. The expressions for $NF_{min}$ and $Y_{opt}$ can be derived for a MOS device by considering a two-port network model for the MOS device. In this model the gate-source terminal is the input port, and the drain-source terminal is the output port. When source admittance presented to transistor ($Y_{s}$) is matched at $Y_{opt}$, the NF has almost $NF_{min}$ ^(11,12).

2.4 Layout Issues

The circuits are designed and fabricated using 65 nm RF CMOS technology. This technology offers six metal layers with two top layers of 0.6$\mu \mathrm{m}$ thick copper. Shield pads for inductors are employed at each port. Fig. 5 shows die photograph of the proposed LNA. Grounded metal underneath the pads prevents loss of the signal power and noise generation associated with the substrate resistance. Ground rings are placed around each transistor at minimum distance to reduce the substrate loss. To minimize parasitic capacitance all transistors are designed by folded structure ⁽⁹⁾. Signal lines were wide enough to meet electro-migration requirements. Ground lines were made wide to provide low impedance paths. The decoupling capacitor was added to bypass high frequency noise from the bias voltage. Grounded guard ring with substrate connection surrounds the inductor to minimize substrate noise. The MIM capacitors are used for high quality factors and the resistors of tantalum nitride thin film are used. Large on-chip bypass capacitors are placed between each $V_{DD}$and ground. The die occupies 0.60${\times}$0.60 mm$^{2}$ including pads and 0.31${\times}$0.35 mm$^{2}$ without pads.