JeongByung-Jun1
JeongJun-Kyo1
SongYu-Min1
LeeHi-Deok1
ChoiHo-Suk2
LeeGa-Won1,*
-
(Department of Electronics Engineering, Chungnam National University, Daejeon 305-764,
Korea
)
-
(2Department of Chemical Engineering and Applied Chemistry, Chungnam National University,
Daejeon 305-764, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Bootstrap, CMOS, fully differential, mirrored-cascode, TIA
I. INTRODUCTION
Recently, amorphous indium-gallium-zinc oxide thin-film transistor (a-IGZO TFT) has
attracted much attention as a most promising switching device in flexible electronics
because of high mobility and good uniformity with low temperature process compared
with Si-based TFTs (1-8). For further improvement of the electrical characteristics of a-IGZO TFT, many researchers
have used plasma treatment as an efficient post-treatment method (9-11). Especially, the plasma treatment on ZnO-based TFTs have been known to control carrier
concentration associated with oxygen vacancies (V$_{\mathrm{O}}$). As a representative
method, Ar plasma treatment can be chosen where the metal and oxygen bond (M$_{\mathrm{O}}$)
breaks by bombardment with a number of Ar ions in the plasma, and the oxygen molecule
is preferentially dissociated by the bombardment due to its relatively high sputtering
yield (15,16). That is, Ar plasma treatment is thought to be an effective method to increase V$_{\mathrm{O}}$.
Since V$_{\mathrm{O}}$ in oxide semiconductors are often referred to as direct or
indirect indicator for free electron concentration, the Ar plasma treatment has been
known to control the electrical properties of a-IGZO TFT (9-11). The conventional Ar plasma treatment has disadvantages that it damages the channel
layer (12-14) and needs high cost vacuum equipment, rendering it difficult to develop into an economic
continuous process.
In this paper, plasma surface treatment at room temperature under air is suggested
to improve the properties of a-IGZO TFT. This process is based on RF Ar plasma exposure
without using a vacuum pump as shown in Fig. 1. Aforementioned, surface Ar plasma treatment can increases V$_{\mathrm{O}}$ and the
channel conductance but V$_{\mathrm{O}}$ also lead to a stability problem because
it acts as a deep trap by capturing the electrons (17-19). To overcome this problem, the suggested Ar plasma is also treated only on the source/drain
(S/D) contact region and the threshold voltage shift (${Δ}$V$_{\mathrm{th}}$) after
constant positive gate bias stress is compared with the one whose whole surface is
exposed to plasma.
II. EXPERIMENT
In this experiment, the bottom gated a-IGZO TFTs were fabricated on the n+ silicon
wafers. 120 nm SiO2 dielectric layer was thermally grown as a gate insulator. Then,
IGZO layer was deposited at room temperature via RF sputter, using an IGZO target
(InO, GaO, ZnO. 2:2:7) and Ar and O2 were used as the reaction gases. The power and
pressure were 100 W/cm$^{2}$ and 5 Pa, respectively. The thickness of IGZO is 55 nm.
After IGZO film deposition, RF Ar treatment was performed for 15 min at 150 W from
5 cm away from the overall IGZO surface (whole region plasma sample). Fig. 1(a) shows the schematic of the Ar plasma equipment. Because the suggested surface treatment
is done at room temperature under air, this process can be used in roll-to-roll process
as shown in the Fig. 1(b). For the comparison, a convention device without surface treatment (base sample)
were also fabricate. For the channel layer patterning, wet etchant of 0.2% HCl solution
was used as an etchant for IGZO layer. The channel width (W) is 100 ${μ}$m and the
channel length (L) is varied to10 ${μ}$m, 20 ${μ}$m, 50 ${μ}$m, and 100 ${μ}$m to
extract contact resistance by the transmission line method (TLM). Next, for the source/drain
(S/D), Ti was deposited by RF sputter which was patterned by lithography and lift-off
process. To investigate the plasma treatment effect on electrical stability, selective
plasma treatment is also done in S/D contract region. In the case of device whose
S/D contact region is exposed to plasma (contact region plasma sample), Ar plasma
treatment was applied for 15 min. before Ti deposition. For the backgate contact,
Al electrode was deposited by RF sputter at back side of silicon wafer. All of the
fabricated devices were annealed in tube furnace at 250~˚C for 1 hour in the air.
The summarized process flow is depicted in Fig. 2.
Fig. 1. (a) The schematic diagram of RF atomistic pressure Ar plasma (APAP) equipment,
(b) A schematic diagram of APAP in a roll to roll process.
Fig. 2. (a) The process flow of the proposed device fabrication, (b) the schematic
of the fabricated a-IGZO TFTs with RF atmospheric pressure Ar plasma (APAP) treatment.
Here, the plasma treatment is done on entire channel region (whole region plasma)
and only on S/D contact region (contact region plasma). The channel width (W) is 100
${μ}$m and length (L) is varied from 10 ${μ}$m to 100 ${μ}$m for contact resistance
extraction.
To investigate the effect of Ar plasma treatment on IGZO active layer, X-ray photoelectron
spectroscopy (XPS) spectra was analyzed. From the fabricated TFTs, the transfer curves
of gate voltage (V$_{\mathrm{GS}}$) - drain current (I$_{\mathrm{DS}}$) is measured
and the electrical parameters such as threshold voltage (V$_{\mathrm{th}}$) and field
effect mobility (${μ}$$_{\mathrm{FE}}$) were compared. The contact resistance was
also extracted by TLM and the electrical reliability of the a-IGZO TFT under the constant
gate bias stress according to the surface treatment was analyzed.
Fig. 3. The transfer curve of the fabricated IGZO TFTs according to the plasma treatment
condition. Whole region plasma is the device whose entire active surface is treated
by RF APAP plasma and contact region plasma is for plasma treated device only on S/D
contact region and base is one without treatment.
III. RESULT & DISCUSSION
1. Electrical Characteristics of a-IGZO TFTs
Fig. 3 shows the transfer curves of the fabricated devices according to the process condition.
I$_{\mathrm{DS}}$ was measured in a dark box as V$_{\mathrm{GS}}$ swept from -10 to
20 V with the drain voltage (V$_{\mathrm{DS}}$) fixed at 10 V. The threshold voltage
(V$_{\mathrm{TH}}$) was estimated by linear fitting of the I$_{\mathrm{DS}}$ versus
V$_{\mathrm{GS}}$ curve in the linear region and the field effect mobility (${μ}$$_{\mathrm{FE}}$)
was calculated using the following Eq. (1)
where C$_{\mathrm{ox}}$ is the gate insulator capacitance, W/L is the aspect ratio
of W to L, and g$_{\mathrm{m}}$ denotes the transconductance (${\partial}$I$_{\mathrm{DS}}$/${\partial}$V$_{\mathrm{GS}}$).
The results show that ${μ}$$_{\mathrm{FE}}$ increases remarkably from 1.69 cm$^{2}$/V${\cdot}$s
(base) to 4.20 cm$^{2}$/V${\cdot}$s in device where the whole channel is exposed to
Ar plasma (whole region plasma). In case of plasma treatment only on contact region
(contact region plasma), ${μ}$$_{\mathrm{FE}}$ also increases to 2.35 cm$^{2}$/V${\cdot}$s.
It can be seen that electrical properties have been improved by increasing the number
of carriers of IGZO by plasma treatment. This result indicates the source/drain contact
resistance is important to electric properties.
Fig. 4. Total resistance (RT) plotted with respect to a-IGZO TFT channel length for
Plasma treatment.
Table 1. Contact resistance comparison of IGZO TFTs parameters according to plasma
treatment region
|
Type
|
Contact resistance
(Source + Drain resistance MΩ)
|
|
Base
|
5.5
|
|
Contact region Plasma
|
1.7
|
|
Channel region Plasma
|
1.6
|
2. Source/drain Contact Resistance
The contact resistance was extracted by TLM. In this experiment, L of transistor is
varied from 10 ${μ}$m, to 100 ${μ}$m with W fixed to 100 ${μ}$m. Fig. 4 shows the total TFT-ON resistance (R$_{\mathrm{T}}$) verse L according to surface
treatment condition. R$_{\mathrm{T}}$ can be written as Eq. (2)
where r$_{\mathrm{ch}}$ is the channel resistance per channel-length unit, and R$_{\mathrm{S}}$
and R$_{\mathrm{D}}$ are the contat resistances associated with the source and drain,
respectively. When plotting RT depending on L with V$_{\mathrm{GS}}$ - V$_{\mathrm{TH}}$
fixing in linear mode, a straight line appears. The slope of the line is rch and y
intercept is the contact resistance (R$_{\mathrm{S}}$ + R$_{\mathrm{D}}$). The longer
the channel length, the less specific the part of the plasma treated contact area.
when the length is 10um, the resistance of the whole region plasma is close to that
of the base.
Table 1 is the extracted contact resistance according to the surface treatment. The contact
resistance decreases remarkably from 5.5 MΩ (base) to 1.7 MΩ by plasma treatment.
In the case of contact region plasma, the resistance was also decreased to 1.6 MΩ
which is similar with whole region treatment. R$_{\mathrm{T}}$ is an important parameter
in controlling the drive current (I$_{\mathrm{DS}}$). Considering that the contact
resistance portion in R$_{\mathrm{T}}$ increases as the size of device decreases as
in high resolution display, the contact region treatment can be thought as an efficient
method to improve the device performance avoiding side effect by the whole region
treatment
(20-22).
Fig. 5. XPS results for the O1s peak for IGZO film according to DPR treatment time
(a) 0 minutes. (conventional), (b) 15 minutes, (c) 30 minutes, (d) comparison of the
atomic ratio of VO and M-O bonding according to the RF plasma treated time.
3. XPS Analysis of IGZO with Plasm Treatment
It is well known that IGZO TFT performance including RT is related with the carrier
concentration or V$_{\mathrm{O}}$ in the IGZO film, XPS O 1s spectra was analyzed
to find out the amount of V$_{\mathrm{O}}$ according to the surface plasma treatment
(21-23). Fig. 5 shows the XPS results according to experimental condition where plasma treatment
time is varied to 0 (Base), 15, and 30 minutes. The O 1s spectrum is deconvoluted
into two Gaussian peaks. The peak near 531.3 ${\pm}$ 0.2 eV (peak 1) is attributed
to O- ions (Oxygen-Metal bonding) and 532.7 ${\pm}$ 0.2 eV (peak 2) is attributed
to V$_{\mathrm{O}}$ (24-26). From the peak fitting, as shown in Fig. 3(d), the atomic ratio of V$_{\mathrm{O}}$ seems to increase from 10.71 to 17.64 % by
15 min. plasma treatment. The amount of V$_{\mathrm{O}}$ increases as the treatment
time becomes longer to 30 min. but the increment is not apparent as the initial increase.
In case of the M-O bonding, it decreases from 89.28 to 82.6 % by plasma treatment
for 15 minutes. The M-O bonding also decreases by small amount as the treatment time
becomes longer to 30 minutes. As mention before, by the preferential sputtering, the
oxygen is being blown away leaving oxygen vacancy, which is favorable to enhancing
the electrical conductance of IGZO TFTs. This process is restricted mainly on IGZO
surface and so, the amount of V$_{\mathrm{O}}$ seems to be saturated as the plasma
process time increases. Oxygen vacancies in metal oxides increase the electrical properties
due to an increase in the number of free carriers, but oxygen vacancies act as deep
trap to trap electrons. Thereby causing a reliability problem of the TFT. So we measured
the reliability of the TFT and confirmed the influence of the plasma process and reliability.
Fig. 6. ID-VG characteristics of plasma TFTs after gate bias stress (a) Base (no treatment),
(b) channel region plasma, (c) contact region plasma.
4. Electrical Reliability of IGZO TFT
V$_{\mathrm{TH}}$ shift (${\Delta}$V$_{\mathrm{TH}}$) is measured under the constant
positive gate bias stress at room temperature with S/D connected to ground. The bias
stress of V$_{\mathrm{GS}}$-V$_{\mathrm{TH}}$ = 5 V were applied and the stress time
was up to 5118 second. I$_{\mathrm{DS}}$-V$_{\mathrm{GS}}$ transfer curve is measured
during the stress as shown in Fig. 6. The positive gate bias stress results in ${\Delta}$V$_{\mathrm{TH}}$ in the positive
direction. In whole region plasma device, ${\Delta}$V$_{\mathrm{TH}}$ is 5.8 V which
is much more than the base device where ${\Delta}$V$_{\mathrm{TH}}$ is 3.8 V. However,
in the contact region plasma one, ${\Delta}$V$_{\mathrm{TH}}$ is 2.8 V similar to
the base one. The positive ${\Delta}$V$_{\mathrm{TH}}$ is known to occur because the
electrons are captured by traps in the gate insulator/IGZO interface and the IGZO
bulk. Because V$_{\mathrm{O}}$ can act as a deep trap, the whole region treatment
device whose amount of V$_{\mathrm{O}}$ is the most is thought to show the worst ${\Delta}$V$_{\mathrm{TH}}$.
On the other hand, in the case of partial plasma treatment on the S/D region, ${\Delta}$V$_{\mathrm{TH}}$
was similar to that of the base device. These results shows that a-IGZO TFT performance
can be enhanced efficiently without deteriorating the electrical reliability by local
plasma treatment.
IV. CONCLUSIONS
To improve the electrical characteristics of a-IGZO TFT, we proposed a surface treatment
of Ar plasma at room temperature under air as an economic continuous process method
compatable to roll-to-roll fabrication. The electrical characteristics of the fabricated
device showed that ${μ}$$_{\mathrm{FE}}$ increased remarkably from 1.69 cm$^{2}$/V${\cdot}$s
(base) to 4.20 cm$^{2}$/V${\cdot}$s (whole region plasma). Base on TLM, it was confirmed
that the contact resistance as well as channel resistance decreases by the suggested
plasma treatment. This improvement is related to the electron concentration and V$_{\mathrm{O}}$.
XPS analysis shows that V$_{\mathrm{O}}$ associated with the free carriers of IGZO
increases by the surface plasma treatment. The electrical reliability of device is
important for backplane display. After the constant gate bias stress, large positive
${\Delta}$VTH is observed in the whole region plasma device but the amount of ${\Delta}$VTH
in contact region device is comparable with the base. Considering ${μ}$FE increases
to 2.35 cm$^{2}$/V${\cdot}$s by the selective S/D contact treatment, ${μ}$$_{\mathrm{FE}}$
can be enhanced without deteriorating the electrical reliability by local plasma treatment.
Therefore, the suggested plasma treatment under air is very promising method for low
cost and high performance IGZO TFT fabrication.
To improve the electrical characteristics of a-IGZO TFT, we proposed a surface treatment
of Ar plasma at room temperature under air as an economic continuous process method
compatable to roll-to-roll fabrication. The electrical characteristics of the fabricated
device showed that ${μ}$$_{\mathrm{FE}}$ increased remarkably from 1.69 cm$^{2}$/V${\cdot}$s
(base) to 4.20 cm$^{2}$/V${\cdot}$s (whole region plasma). Base on TLM, it was confirmed
that the contact resistance as well as channel resistance decreases by the suggested
plasma treatment. This improvement is related to the electron concentration and V$_{\mathrm{O}}$.
XPS analysis shows that V$_{\mathrm{O}}$ associated with the free carriers of IGZO
increases by the surface plasma treatment. The electrical reliability of device is
important for backplane display. After the constant gate bias stress, large positive
${\Delta}$VTH is observed in the whole region plasma device but the amount of ${\Delta}$VTH
in contact region device is comparable with the base. Considering ${μ}$FE increases
to 2.35 cm$^{2}$/V${\cdot}$s by the selective S/D contact treatment, ${μ}$$_{\mathrm{FE}}$
can be enhanced without deteriorating the electrical reliability by local plasma treatment.
Therefore, the suggested plasma treatment under air is very promising method for low
cost and high performance IGZO TFT fabrication.
ACKNOWLEDGMENTS
This work was supported by a National Research Foundation of Korea (NRF) grant, funded
by the Korea government (MSIP) (2017R1D1A1B03033601), and by the National Research
Foundation of Korea (NRF) grant, funded by the Korea government (MSIT) (NRF-2019R1A2C1084717).
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Author
received a B.S. degree in Physics in 2017 and is currently working toward an M.S.
degree in the Department of Electronics Engineering from the Chungnam National University,
Daejeon, Korea.
His research interests include Fabrication high performance oxide thin film transistor.
received a B.S. degree in electronic engineering in 2016 and is currently working
toward an integrated Ph.D. program in the Department of Electronics Engi-neering from
the Chungnam National University, Daejeon, Korea.
His research interests. include flash memory, oxide thin film transistor.
is currently studying toward an B.S. degree in the Department of Electronics Engi-neering
from the Chungnam National University, Daejeon, Korea.
His research interests include reliability and analysis of flash memory.
received B.S., M.S., and Ph.D. degrees from Korea Advanced Institute of Science and
Technology (KAIST), Daejeon, Korea, in 1990, 1992, and 1996, respectively, all in
electrical engineering.
In 1993, he joined LG Semicon Co., Ltd. (currently SK hynix Semiconductor), Cheongju,
Korea, where he was involved in the development of 0.35-, 0.25-, and 0.18-μm CMOS
technologies, respectively.
He was also responsible for the development of 0.15- and 0.13-μm CMOS technologies.
Since 2001, he has been with Chungnam National University, Daejeon, and now is Professor
with the Department of Electronics Engineering.
From 2006 to 2008, he was with the University of Texas, Austin, and SEMATECH, Austin,
as a Visiting Scholar.
His research interests are nanoscale CMOS technology and its reliability physics,
silicide technology, and test element group design.
His research interests also include sensitivity improvement of sensors, and development
of high performance sensors.
Dr. Lee is a member of the Institute of Electronics Engineers of Korea.
He received the Excellent Professor Award from Chungnam National University in 2001,
2003 and 2014.
received B.S., M.S., and Ph.D. degrees in Electrical Engineering from Korea Advanced
Institute of Science and Technology (KAIST), Daejeon, Korea, in 1994, 1996, and 1999,
respectively.
In 1999, she joined Hynix Semiconductor Ltd. (currently SK Hynix Semiconductor Ltd.)
as a senior research engineer, where she was involved in the development of 0.115-Se
and 0.09—S DDR II DRAM technologies.
Since 2005, she has been at Chungnam National University, Daejeon, Korea, as a Professor
with the Department of Electronics Engineering.
Her main research fields are flash memory and flexible display technology including
fabrication, electrical analysis, and modeling.