I. INTRODUCTION

With the advent of the fourth industrial revolution, industries such as artificial intelligence ($A.I.$), the Internet of things ($IoT$), self-driving cars and big data are emerging. As this new industry appears, it leads to mass of data distribution and large capacity contents consumption. In accordance with this demand, memory capacity increases and the need for server investment grows ^(1,2). In order to satisfy this, research on high-performance 3D NAND flash memory is being actively conducted. High-performance memory requires high degree of integration, low bit cost, and low inter-cell interference. The 3D NAND flash memory can satisfy this demand ^(3,4).

As degree of integration increases, problems arise in physical ($degradation$ $of$ $lithography$ $pattern$), electrical ($shoot$ $channel$ $effect,$ $gate$ $induced$ $drain$ $leakage$), and reliability aspects ($retention$ $decrease$ $due$ $to$ $electronic$ $loss$). In particular, the degradation problem of retention caused not only vertical charge loss in the 2D structure but also other problems as the structure of the memory changed to 3D structure.

As shown in Fig. 1, the 3D structure shares the ONO layer. As a result, charge migration occurs not only vertically but also laterally. Migration within the charge trapping layer ($CTL$) can be a serious problem due to the shared ONO structure. As a result, it is necessary to further consider the leakage path for the stored charge in $CTL$. Additional migration may cause retention degradation for the cell ^(5,6). Therefore, it should be considered for the reliability evaluation of the 3D memory device.

Charge migration of 3D NAND flash memories has been studied steadily ^(7-9). However, these studies indirectly explain lateral charge migration through simulation or electrical characteristic. Therefore, this study proposed a test pattern for charge migration analysis. Using the proposed test pattern, the vertical and lateral charge migration were separated. In addition, we will analyze the mechanism of each charge migration using the separated values.

II. EXPERIMENT

To fabricate SONOS structure cells for application in non-volatile memory ($NVM$), the 7 nm silicon dioxide ($SiO_{2}$) dielectric for tunneling oxide layer was thermally grown on a prime grade p-type Si substrate with high-purity oxygen gas via a dry oxidation furnace. The silicon nitride ($Si_{3}N_{4}$) as a $CTL$ and the SiO₂ blocking oxide layer were deposited by low-pressure chemical vapor deposition ($LPCVD$). The 7 nm Si₃N₄ $CTL$ and 15 nm blocking oxide layer are considered in this study. In addition, the 100 nm titanium ($Ti$) electrode was deposited for the memory cells. Finally, Al was deposited by RF sputter at back side of silicon wafer for the contact body. Fig. 2 shows the fabricated SONOS capacitor structure.

Fig. 3 shows the gate shape of the test pattern proposed in this study.

Fig. 3(a) shows an antenna-shaped pattern to increase the perimeter length to maximize lateral charge migration. Fig. 3(b) is a mesh-shaped pattern designed to improve process stability and evaluate interference between metal lines compared to antenna-shaped pattern. Each pattern was split in width, distance, area ratio, and perimeter ratio. A square pattern with the same area as the test pattern was additionally designed for reference measurement on each test pattern.

Fig. 4 is a schematic diagram showing the movement of electrons in the CTL according to the pattern shape. In case of test pattern, the lateral charge migration is maximized because the perimeter length is designed longer than the square pattern of the same area. Under the same measurement conditions, the charge loss in the square pattern is mostly caused by vertical charge migration. In the test pattern, the charge loss will increase because both vertical and lateral charge migration occur simultaneously. Then, the actual lateral charge migration can be obtained by the difference between the charge loss measurements in the test pattern and the square pattern.

The capacitance-voltage ($C$-$V$) and retention analysis were measured on fabricated capacitors using a Hewlett Packard 4284A precision LCR meter. Retention characteristics for the programmed state were obtained by monitoring the flat band voltage ($V_{FB}$) shift with respect to its initial value and retention tests were performed at room temperature (20 ℃) to 125 ℃.

III. SIMULATION RESULTS

Fig. 5 shows the $C$-$V$ analysis according to temperature. The same program voltage ($V_{PRG}$) was applied to match the programmed position. After the program, the temperature of the device was increased and the $V_{FB}$ shift was confirmed by measuring the $C$-$V$ at 10 minute intervals from 0 to 20 minutes. The retention measurement shows that the $V_{FB}$ shift to the left over time. At higher temperature, the more $V_{FB}$ shift was observed.

$V_{FB}$ was extracted to 80 % of the maximum capacitance. Charge loss is expressed as a percentage and the equation is as follows.

Fig. 6 shows the charge loss according to the area ratio in the square pattern and perimeter ratio in the antenna-shaped pattern. The area and perimeter corresponding to "1" are 25764 µm² and 6344 µm, respectively. In the square pattern, it is assumed that the vertical migration occurs dominantly because the area-to-perimeter is very small. Therefore, Fig. 6(a) shows that the amount of charge loss is almost constant as the area increases. When the temperature was increased, it was confirmed that the amount of charge loss was increased. Fig. 6(b) shows the charge loss measured in the antenna-shaped pattern at a temperature of 125 ℃. As the perimeter increases, the charge loss increases linearly. It can be expected that that the movement of the electron by the lateral charge migration increased with increasing perimeter length.

Fig. 7 shows the charge loss due to the lateral charge migration according to perimeter length at 125 ℃ using the results in Fig. 6. The lateral charge loss was extracted using the difference between Fig. 6(a) and (b).

In Fig. 7, as perimeter ratio increases, lateral charge loss increases. When the perimeter ratio is small, it is only 5 % of the total charge loss, but when the perimeter ratio is increased to 9, it increases to 25 %.

Fig. 8 shows the $V_{FB}$ shift of the mesh-shaped pattern over time. $V_{FB}$ shift was measured by varying the length of one side of the inner square. As the length of one side increases, the length of the lateral charge migration increases. Therefore, as the length of one side increases, the $V_{FB}$ shift increases. Therefore, the proposed test pattern is very effective for reliability evaluation because it can maximize the lateral charge migration effect.

Fig. 9 shows a graph comparing the effects of lateral and vertical charge loss with decreasing channel length. The effect of lateral charge migration increases as channel length decreases. In this study, the channel length is um level. Because the area of contact with the channel is very large, the vertical charge loss appears larger than lateral charge loss. However, if the channel length is decreased to nm level, lateral charge migration will be the main cause of charge migration ⁽¹⁰⁾. Therefore, lateral migration is more important than vertical migration in the reliability problem of 3D SONOS NAND flash memory.

To evaluate the activation energy for the charge migration, the temperature dependence of charge loss are measured in antenna-shaped pattern and square pattern as shown in Fig. 10(a), which is redrawn to Fig. 10(b) to apply to the Arrhenius equation. The Arrhenius equation used is as follows.

The activation energy in the square pattern ($E_{A,vertical}$) where the vertical migration is main factor for the charge loss was calculated as 0.238 eV. And the activation energy in the test pattern ($E_{A,Lateral}$) where only the lateral migration is considered by subtracting the vertical charge loss was calculated as 0.058 eV. It is noticeable that $E_{A,Lateral}$ is very smaller than $E_{A,vertical}$ and similar results have been reported based on the simulation by other research group ^(11,12). This is because lateral charge migration occurs above the conduction band. The electrons in the shallow traps move up the conduction band by heat, and the electrons in the conduction band can move easily. Therefore, it can be expected for electron in the conduction to diffuse with a relatively small energy, which is illustrated in Fig. 11 by the lateral charge migration by the conduction band diffusion.

IV. CONCLUSIONS

In this study, we proposed a test pattern for analyzing the charge migration in 3D SONOS flash memory. For the analysis, a capacitor with ONO structure was fabricated, and C-V curve and retention analysis were performed according to the temperature. Vertical charge loss was measured by retention measurement in the conventional square pattern, and total charge loss was measured by increasing the perimeter ratio using the test pattern. And, substantial lateral charge losses were extracted using the difference between the square pattern and the test pattern. In addition, the activation energy of lateral and vertical charge migration was extracted using the Arrhenius equation. From the extracted activation energy, lateral charge migration is modeled by the conduction band diffusion. Because the suggested test pattern can measure each value for the lateral and vertical migration occurring in the 3D SONOS flash memory, it is expected that a clear analysis of the reliability problem that can be caused by the charge migration is possible.