I. INTRODUCTION

Dynamic random access memories (DRAM) have an important role in various microelectronic systems such as computer and mobile phone. As the size of a DRAM cell is scaled down, it becomes more difficult to integrate a capacitor with a transistor. Thus the capacitorless one transistor (1T) DRAM cell has attracted much attention, thanks to its merits over a conventional one transistor and on capacitor (1T1C) DRAM cell ^(1-3). However, the limitation of retention time makes the applicability of the 1T DRAM cell narrow. In the past ten years, various device structures attempting to overcome the retention time degradation due to silicon film thickness downscaling such as ZRAM, A2RAM, and twin gate tunneling field effect transistor (TGTFET) were proposed for the 1T DRAM ^(4-6). Within various structures, TGTFETs have attracted attention due to their high retention characteristics in 1T DRAM ⁽⁶⁾. The goal of this paper is to propose a novel 1T DRAM cell based on TGTFET for the further improvement of data retention characteristics by adopting localized partial insulator (LPI) structure ⁽⁷⁾. Insertion of the LPI can enhance retention time due to the large energy barrier. In addition, optimization method with proposed is introduced with variation of LPI parameter.

II. DEVICE STRUCTURE

The schematic diagram of the proposed 1T DRAM is shown in Fig. 1.

Proposed device has the p-I -n channel and twin gate structure. Intrinsic channel forms virtual junction by two different gates which have different dopants. Each gate consists of N + poly silicon and P + poly silicon.

Each of gate length (L_G1, L_G2), source and drain length (L_S, L_D), and silicon body thickness (T_body) are 100 nm, 50 nm and 20 nm respectively. Silicon dioxide is used as the gate dielectric and its thickness (T_ox) is 3 nm.

Doping concentration of source and drain region is 1 × 10²⁰ cm^-3 and intrinsic channel region is 1 × 10¹⁵ cm^-3 respectively. Three LPIs are located at the center of channel and source/drain junction area. Barrier oxide length (L_barrier) and barrier oxide thickness (T_barrier) are 15 nm and 4 nm.

Since the proposed device has an asymmetric gate, it is difficult to manufacture it with a conventional MOSFET fabrication process. In order to fabricate the proposed device, a fin-type silicon channel must be fabricated as shown in Fig. 2(a). The n type silicon gate and the p type silicon gate are sequentially formed through separated photolithography processes as shown in Fig. 2(a) to Fig. 2(e). Although omitted in the Fig. 2, the gate dielectric must be additionally formed through the atomic layer deposition (ALD) process after etching the gate formation region. The LPI structure can be formed by silicon nano trench etching, filling the dielectric and then planarization process. Specific process sequences and confirmation of feasibility can be investigated with further studies.

III. RESULTS AND DISCUSSIONS

Before analyzing the characteristics of 1T DRAM, basic electrical characteristics of transistor operation were confirmed as shown in Fig. 3. A number of physical models including non local band-to-band tunneling, carrier mobility models, Auger recombination model, Shockley-Read-Hall (SRH) recombination model have been applied simultaneously in cooperation for more accurate simulation results. When a current flows in the channel region, current does not flow in a portion where LPI is inserted. It is possible to predict that the presence of LPI can cause the on-current difference of 1T DRAM by the difference of the current conduction region. However, the on-current level is different due to the difference in the current conduction region, but the difference is not significant. A set of bias schemes for the memory operations of the proposed 1T DRAM is provided in Table 1. The change in memory state is made by the modulation of barrier heights of the channel segments restricted by the LPIs, by V_GS1, V_GS2, and V_DS.

Fig. 4(a) shows lateral energy band diagram in the channel region with zero bias condition. Due to the different workfunction in the twin gate region, virtual junction is formed in the channel region. The region under the n+ poly gate (gate 1) contains electron and another region (gate 2) contains hole respectively. The energy band diagram is extracted from program operation and shown in Fig. 4(b). Electron tunneling occurs through narrow energy barrier between the channel region under gate2 and drain region.

As a result of the electron tunneling, holes accumulate in the channel area under gate2. When the holes accumulate, the energy barrier decreases when electrons injected from the source move to drain during read operation, resulting in an increase in read current.

Fig. 4(c) shows the energy band diagram which is extracted during erase operation. The energy band is flattened by the positive bias applied to Gate 2, causing the stored holes to exit the drain region.

As a result, the energy band diagram of the channel goes back to its initial state.

Fig. 5(a) shows the channel energy band diagram with initial state and hold states. In the hold 1 state as shown in Fig. 5(a), Energy barrier under the gate 2 region maintains low height that allows a large current. On the contrary, in the state of hold 0, it can be seen that the channel maintains a curved energy band where a current is prohibited.

The program - hold - read - hold - erase - hold - read - hold sequence used for the ‘1’ and ‘0’ states in the proposed 1T DRAM memory operation is provided in Fig. 6. Detailed bias conditions for memory operation are listed in Table 1. The change of the memory states is performed by modulation of virtual junction with twin gate bias.

In the proposed memory, '1' state is defined as the state where holes are stored in the hole storage region and the barrier under gate 2 is lowered. When the read bias is applied, a current level is high.

Conversely, in the '0' state, holes are not stored in the hole storage region, so that the original junction is maintained.

As a results a current level maintains low level. Without the LPI structure, the current on / off ratio of read 1 and read 0 is 1.46 × 10⁴ A/A. If there is an LPI structure, the current on/off ratio of read 1 and read 0 is 5.65 × 10⁵ A/A.

In the proposed 1T DRAM, the insertion of LPI also improves the on / off current ratio.

LPI can reduce the amount of holes lost in the hole storage area. This amount of hole dissipation is related to the retention characteristics of the device. A method of measuring retention characteristics is provided in Fig. 7.

The retention time of the proposed 1T DRAM is defined as the time it takes for the I₁ / I₀ ratio to become 10 times when a hold bias is applied after a program or erase operation. Retention time of suggested device with LPI records 547 ms which is significantly increased value compared with 104 ms in the 1T DRAM without LPI. The effect of LPI on retention time is enhancement of hole storage capability. When holes are stored in 1T DRAM, hole leakage can occur between hole storage region and drain region. Large energy barrier provided by silicon dioxide in LPI effectively prohibits hole leakage current between hole storage region and drain region. Fig. 8 shows hole leakage current distribution of hold 1 state. Most of hole leakage are concentrated in surface area of the junction. As shown in Fig. 8, there is no current in LPI region and relatively small amount of hole leakage current flows on the top surface of LPI region.

In order to optimize the effect of LPI, the results of retention time with body thickness and LPI length variation are presented in Fig. 9. In the case of reducing the body thickness from 20 nm to 10 nm, retention characteristics increased with LPI as shown in Fig. 9(a). Considering this result, the optimization according to the LPI length variation was investigated with the 10 nm body thickness.

As shown in Fig. 9(b), the retention time increases until the barrier length increases to 8 nm. However, if the barrier length increases above a certain value, the read current cannot be extracted. As the LPI length approaches the channel thickness, the current conduction region decreases. As a result, read 1 current is also drastically reduced, and normal DRAM operation is not available. Therefore, holes cannot be accumulated, and thus retention time is also close to zero. As can be seen from the above results, increasing the barrier length helps to increase the reliability of the device but should be performed within a certain range.

IV. CONCLUSIONS

reliability characteristics in 1T DRAM device with TGTFET. Insertion of LPI in the boundaries of junction area has its advantages of the fact that it prohibit movement of stored charge. Retention time of suggested device with LPI records 547 ms which is significantly increased value compared with 104 ms in the 1T DRAM without LPI. The optimization of the device has been studied with LPI length variation. As the length of LPI structure increased, retention time increased up to certain value. Increasing the LPI length beyond a certain level interrupted the current flow, resulting in deterioration of the device's operation. The proposed device is considered to be a strong candidate for low power, high reliability 1T DRAM.