I. INTRODUCTION

As the bandwidth of mobile devices, including displays and cameras, grows rapidly, the protocol of the mobile industry process interface (MIPI) has been widely used to reduce the power consumption and EMI noise ^(1-3). The D-PHY and C-PHY specifications have been used for the camera serial interface (CSI) and display serial interface (DSI) of the MIPI. The MIPI D-PHY version 2.0 specification supports four data lanes with a clock lane for a source-synchronous clocking scheme ⁽⁴⁾. The total bandwidth of the MIPI D-PHY version 2.0 specification is 20 Gb/s using ten pins while each data lane provides a data rate of 5.0 Gb/s. Meanwhile, the MIPI C-PHY supports three embedded clock and data lanes where each lane transmits three-phase symbols using three wires. It is based on three-phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios. The MIPI C-PHY version 1.1 specification is targeting 3 Gsymbol/s/lane and its total bandwidth is specified to be 20.52 Gb/s using three embedded clock and data lanes ⁽⁵⁾.

The aforementioned PHY technologies of the MIPI are becoming increasingly important for higher bandwidth and pin efficiency according to a CMOS image sensor (CIS) with more than 20 Megapixels has been developed for mobile camera applications ⁽⁶⁾. Furthermore, the recently announced high-resolution CIS supports both the MIPI D-PHY and C-PHY specifications to support various mobile applications. Therefore, a frame grabber that can acquire the video or image data supplied from a camera sensor module should support both the MIPI D-PHY and C-PHY specifications. Fig. 1 shows a conceptual diagram of a frame grabber using a field-programmable gate array (FPGA) for the MIPI CSI-2. Generally, a FPGA does not support the scalable low-voltage singling (SLVS) interface used in the MIPI D-PHY and C-PHY. Thus, a FPGA-base frame grabber requires a receiver bridge chip to convert the high-speed data of SLVS of the MIPI CSI-2 into the low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip, as shown in Fig. 1^(7-9). In addition, a MIPI receiver bridge chip supporting the D-PHY and C-PHY specifications is required for evaluation of the CIS using both the MIPI D-PHY and C-PHY.

Fig. 1. Conceptual diagram of FPGA-based frame grabber using MIPI receiver bridge chip.

In this work, a single receiver bridge chip, which fully supports the protocols of the D-PHY version 2.0 and the C-PHY version 1.1 for the MIPI CSI-2 specification, is proposed for a FPGA-based frame grabber ⁽¹⁰⁾. The proposed MIPI receiver bridge chip is used for the high-speed interface link between the MIPI embedded chip and the FPGA chip. Section II presents the operation, including the block and timing diagrams of the MIPI D-PHY and C-PHY receiver bridge chip proposed in this paper. Furthermore, it describes high-speed receivers with equalizer and a clock recovery with deglitch circuit for the improvement of the signal integrity in the high-speed receiver circuit for the SLVS interface of the MIPI D-PHY and C-PHY. Section III presents the measurement results of the implemented MIPI DPHY and C-PHY receiver bridge chip. Finally, Section IV provides the conclusion of this paper.

II. MIPI D-PHY AND C-PHY RECEIVER BRIDGE CHIP SUPPORTING CSI-2

Fig. 2 shows the block diagram of the proposed MIPI D-PHY and C-PHY receiver bridge chip. The MIPI D-PHY receiver consists of four data lanes and one clock lane supporting high-speed mode and low-power mode operations. For high-speed mode operation, each data lane supports a data rate of 5 Gb/s and consists of a high-speed receiver ($\textit{D-PHY RX}$) supporting the SLVS interface, a 1-to-8 deserializer (1-to-8 $\textit{Deserializer}$), a byte synchronizer ($\textit{Byte Detector}$) for frame-lock operation for interfacing with the FPGA. The block $\textit{Byte Detector}$ is only included in the first data lane. Its result $\textit{Byte Sync}$ is provided to the other data lanes and is also output to the FPGA such that the FPGA senses the byte synchronization status of the MIPI CSI-2 interface. The clock lane has the same high-speed receiver used in the data lane and a programmable delay circuit ($\textit{Skew Calibration}$) for optimal sampling between the data lanes and the clock lane, When all four data lanes are active, ten pins are used for high-speed operation of four data lanes and one clock lane, and 32 LVCMOS signals are activated and supplied to the FPGA along with the byte clock of $\textit{CLK}$$_{BYTE}$.

Fig. 2. Block diagram of proposed MIPI D-PHY and C-PHY receiver bridge chip.

The MIPI C-PHY receiver consists of a high-speed receiver ($\textit{C-PHY RX}$) for receiving the signals with three voltage levels, a clock recovery with deglitch circuit ($\textit{Clock Recovery}$), a 3-to-21 deserializer, and a 21-to-16 demapper for receiving data with a symbol rate of 3~Gsymbol/s/lane. According to the protocol of the MIPI C-PHY version 1.1, the MIPI C-PHY receiver supports three lanes. Each lane operates independently of the other lanes and outputs the signal $\textit{FLAG}$$_{LANE\#}$ indicating the frame lock of each lane. When all three lanes are active in the case of the MIPI C-PHY receiver, nine pins are used for high-speed operation and all 48 LVCMOS signals are used for the parallel interface with the FPGA.

Ten pins for receiving the high-speed SLVS data and 48 pins for transmitting the LVCMOS data are shared for the MIPI D-PHY and C-PHY receivers, respectively. The proposed MIPI receiver bridge chip provides data rates of over 20 Gb/s per chip for the MIPI D-PHY with four data lanes and the C-PHY with three lanes, respectively. For low-power mode operation, the proposed MIPI receiver bridge chip has nine pins. In the case of the MIPI C-PHY receiver, all nine pins with transmitter and receiver for the LVCMOS signaling are used for the three data lanes. For low-power mode operation of the MIPI D-PHY receiver, eight of nine pins are used for four data lanes.

1. Circuit and Operation of MIPI D-PHY Receiver

The circuits for the MIPI D-PHY receiver are designed based on the circuits for the MIPI D-PHY version 1.2 specification reported in the prior literature ⁽⁹⁾ because the functional protocol of the MIPI D-PHY version 2.0 is the same as for the version 1.2. However, a high-speed receiver for the MIPI D-PHY version 2.0 specification should have the bandwidth to achieve a data rate of 5.0 Gb/s/lane. The high-speed receiver ($\textit{D-PHY RX}$) of each data lane which receives an input signal of a SLVS consists of two amplifiers to increase its bandwidth, as shown in Fig. 3. The first amplifier is a common-gate level shifter with a continuous-time linear equalizer for the pre-emphasis ⁽⁹⁾. The second amplifier of a differential amplifier with source degeneration performs the de-emphasis by reducing the voltage gain at the low frequency ⁽¹⁾. Fig. 4 shows the simulated performance of the high-speed receiver. This simulation was performed by using a point-to-point channel with a voltage-gain degradation of 20.3 dB at a frequency of 2.5 GHz, as shown in Fig. 4(a). When the eye opening of the input signal of $\textit{D-PHY RX}$ transmitted through this channel is 41.6 mV and 80.7 ps, as shown in Fig. 4(b), the equalization of the $\textit{D-PHY RX}$ reduces the peak-to-peak time jitter from 64.5 ps to 16.1 ps, as shown in Fig. 4(c) and (d) .

Fig. 3. Circuit diagram of high-speed receiver for MIPI D-PHY receiver.

Fig. 4. Simulated eye diagram of first stage of D-PHY RX at 5 Gb/s/lane (a) frequency response used in simulation (b) input signal (c) output signal w/o equalization (d) output signal w/ equalization

2. Circuit and Operation of MIPI C-PHY Receiver

The MIPI C-PHY specification uses a 3-level clock-embedded differential signal with SLVS over three wires for high-speed operation. The proposed 3-Gsymbol/s/ lane MIPI C-PHY receiver, which performs the reception function for one lane, includes three high-speed receivers ($\textit{C-PHY RXs}$) with a linear equalizer and a clock recovery ($\textit{Clock Recovery}$) for the first stage, as shown in Fig. 5. Each $\textit{C-PHY RX}$ uses two input signals as a differential input signal among three transmitted signals $\textit{RXA}$, $\textit{RXB}$, and $\textit{RXC}$. The clock recovery generates a clock signal $\textit{CLKA}$ by generating a rising or falling edge when sensing a transition of at least one of the three received signals $\textit{DOA}$, $\textit{DOB}$, and $\textit{DOC}$.

Fig. 5. First stage of MIPI C-PHY receiver.

Fig. 6. High-speed receiver for MIPI C-PHY receiver (a) block diagram, (b) circuit diagram of first amplifier.

The receiver circuit using a common-gate level shifter shown in Fig. 3 can be used as a high-speed receiver for the MIPI C-PHY receiver because the input signal of the MIPI C-PHY receiver is also a SLVS with low common-mode voltage similar to that of the MIPI D-PHY receiver ⁽¹¹⁾. However, because the input signal of the common-gate level shift circuit is connected to the source modes of $\textit{MN1}$ or $\textit{MN2}$, the input impedance and voltage gain of the high-speed receiver circuit vary according to the common-mode voltage of the input signal. In this case, the input impedance and voltage gain of the high-speed receiver circuit using a common-gate level shifter can be constantly maintained by controlling the voltage levels of $\textit{BIASN1}$ and $\textit{BIASN2}$ according to the static change of the input common-mode voltage ⁽¹²⁾. However, in the case of the MIPI C-PHY receiver, the input common-mode voltage of the three high-speed receiver circuits changes continuously in accordance with the input signal. This is because two of the three signals $\textit{RXA}$, $\textit{RXB}$, and $\textit{RXC}$, having different voltages, are input to each high-speed receiver circuit, as shown in Fig. 5. This results in the deterioration of signal integrity due to input impedance mismatches and changes in voltage gain.

Fig. 6(a) shows the block diagram of the high-speed receiver circuit for the MIPI C-PHY receiver. The high-speed receiver circuit, $\textit{C-PHY RX}$, consists of three differential amplifiers to increase the bandwidth and voltage gain while reducing the effect on the variation of the input common-mode voltage. The first differential amplifier uses an input stage with P-type metal-oxide-semiconductor transistors instead of a common-gate level shifter, to receive the SLVS input signal with a low common-mode voltage, and to have an infinite impedance independent on the voltage level of the input signal. Fig. 6(b) shows the circuit diagram of the first stage of the $\textit{C-PHY RX}$. It has an architecture based on a current mirror amplifier using an active inductor to increase the bandwidth and to perform the equalization, although the voltage gain is relatively small. The voltage gain of the first amplifier of the $\textit{C-PHY RX}$ is defined by Eq. (1) at low frequency. As the operation frequency increases, it is increased by the operation of the active inductive load including the resistor $\textit{R}$$_{A}$, as shown in Eq. (2).

(1)

$\begin{align} A_{V(Low\,\,Freq.)}&=g_{mP0}\cdot \frac{1}{g_{mN0}}\cdot g_{mN1}\cdot \left(r_{oN1}\left\| \frac{1}{g_{mN2}}\right.\right) \\ \end{align}$

(2)

$\begin{align} A_{V(High\,\,Freq.)}&=g_{mP0}\cdot \frac{1}{g_{mN0}}\cdot g_{mN1}\cdot \left(r_{oN1}\left\| R_{4}\right.\right)\cdot \left(1+\frac{1}{g_{mN1}}\right) \end{align}$

where $\textit{g}$$_{m}$ and $\textit{r}$$_{o}$ are the transconductance and output resistance of the small-signal models of each transistor, respectively, and the body effect is not considered in both equations. The equalization for the first amplifier of the $\textit{C-PHY RX}$ is performed by changing the voltage gain of the first amplifier of the $\textit{C-PHY RX}$ according to the frequency change, as shown in Eqs. (1, 2).

The second amplifier of the $\textit{C-PHY RX}$ shown in Fig. 6(a) is a differential amplifier with source degeneration for common-mode rejection and equalization. Since the proposed MIPI receiver bridge chip used in the frame grabber should support an interface with a long channel for the test environment of the camera module, additional equalization is performed to improve the signal integrity even if the first amplifier performs the equalization. Finally, the third amplifier of the $\textit{C-PHY RX}$ converts the received differential signal into a single-ended signal while additionally eliminating the effect on the continuously changing input common-mode voltage.

Fig. 7. Simulated eye diagram of first stage of C-PHY RX at 3 Gsymbol/s/lane (a) frequency response used in simulation, (b) input signal, (c) output signal w/o equalization, (d) output signal w/ equalization.

Fig. 7 shows the simulated results performed to evaluate the performance of the first amplifier of the $\textit{C-PHY RX}$. Fig. 7(a) is the frequency response of the channel used in this simulation. This channel is a point-to-point channel with a voltage-gain degradation of 10.6 dB at a frequency of 1.5 GHz. The input signal of the $\textit{C-PHY RX}$ transmitted through this channel has the eye opening with 80 mV and 190 ps, as shown in Fig. 7(b). The equalization using the active inductor load in the first amplifier of the $\textit{C-PHY RX}$ increases the voltage eye opening of 35 mV and reduces the peak-to-peak time jitter of 14.3 ps, as shown in Fig. 7(c) and (d).

Fig. 8. Clock recovery (a) block diagram, (b) circuit diagram of short pulse generator, (c) timing diagram.

Fig. 8(a) shows the clock recovery with deglitch circuit which generates a clock signal of 1.5 GHz from the three received data of 3 Gsymbol/s/lane ⁽¹¹⁾. The proposed clock recovery has an architecture of a dynamic latch-based toggle flip-flop. The short pulse generator ($\textit{PG}$) shown in Fig. 8(b) consists of an edge detection circuit using an exclusive OR/NOR gate and a transmission gate. It senses the transitions of the three received signals $\textit{DOA}$, $\textit{DOB}$, and $\textit{DOC}$, and activates the dynamic latch of the clock recovery. The clock recovery generates a clock signal that inverts the previous state of the $\textit{CLK}$ when a transition of one or more of the three received signals is detected, as shown in Fig. 8(c). Glitch noise can be generated by detecting erroneous transitions due to delay mismatches of three channels or three high-speed receivers. In this work, the deglitch circuit consisting of a delay line located in the feedback path of the clock recovery removes this glitch noise by delaying the inversion of the state of the $\textit{CLK}$. Fig. 9 shows that the glitch noise is removed using the deglitch circuit. This simulation was performed at an operation speed of 1~Gsymbol/s/lane to verify the functional operation of the proposed clock recovery with deglitch circuit when the maximum delay mismatch among the three received signals is approximately 100 ps.

Fig. 9. Simulated results of clock recovery at 1 Gsymbol/s/lane (a) w/o deglitch circuit, (b) w/ deglitch circuit.

Fig. 10. Digital block including 3-to-21 deserializer for MIPIC-PHY receiver (a) block diagram, (b) timing diagram for flip operation.

Fig. 10(a) and (b) show the conceptual block and timing diagrams to explain the operation of the 3-to-21 deserializer, including the decoder, seed detector, and demapper, for the proposed MIPI C-PHY receiver. To simplify the representation and description of the timing diagram, Fig. 10(b) shows the timing diagram for flip operation among the three operations for the MIPI C-PHY receiver. First, the signals $\textit{DOA}$, $\textit{DOB}$, and $\textit{DOC}$, which are the output signals of the three high-speed receivers $\textit{C-PHY RXs}$, are supplied to the decoders for the flip, rotate, and polarity operations. Each decoder samples the received data at the rising and falling edges of the recovered clock signal $\textit{CLKA}$ to support double data-rate operation and it performs the decoding process required in the protocol of the MIPI C-PHY version 1.1. The output signals of each decoder are parallelized to the 8-bit data ($\textit{DC[7:0]}$) using two 4-bit shifter registers and one 8-bit shifter register. The signals $\textit{DF_EVEN}$ and $\textit{DF_ODD}$ shown in Fig. 10(a) are the output signals of the flip decoder. By using the seed detector composed of exclusive OR gates and AND gates, the signal $\textit{DC}$$_{FLIP}$$\textit{[6:0]}$ or $\textit{DC}$$_{FLIP}$$\textit{[7:1]}$ is compared with the predetermined seed data ($\textit{SEED}$$_{FLIP}$$\textit{[6:0]}$) to perform a frame-lock operation. The signal $\textit{SEED}$$_{FLIP}$$\textit{[6:0]}$ is set to 7b’0111110 in the MIPI C-PHY version 1.1 specification. Fig. 10(b) shows the case where the signal $\textit{DC}$$_{FLIP}$$\textit{[6:0]}$ and the signal $\textit{SEED}$$_{FLIP}$$\textit{[6:0]}$ coincide each other. When the signal \textit{DC}$_{FLIP}$$\textit{[6:0]}$ is equal to the signal $\textit{SEED}$$_{FLIP}$$\textit{[6:0]}$, the block $\textit{Seed Detector}$ sets the flag signal $\textit{FLAG}$$_{FLIP}$ high. The final flag signal $\textit{FLAG}$ for the frame lock is enabled when the three flag signals $\textit{FLAG}$$_{FLIP}$, $\textit{FLAG}$$_{ROTATE}$, and $\textit{FLAG}$$_{POLARITY}$ are set high. Then, the frame clock $\textit{CLK}$$_{FRAME}$ for the 3-to-21 deserialization and the 21-to-16 demapper is generated by dividing the clock signal $\textit{CLKA}$ frequency by 3.5 from in synchronization with the rising edge of $\textit{FLAG}$, as shown in Fig. 10(b). The deserialized 21-bit data $\textit{DM}$$_{FLIP}$$\textit{[6:0]}$, $\textit{DM}$$_{ROTATE}$$\textit{[6:0]}$, and $\textit{DM}$$_{POLARITY}$$\textit{[6:0]}$ are converted into the 16-bit parallel data $\textit{P}$$_{CPHY}$$\textit{[16:0]}$ by using the 21-to-16 demapper supporting the protocol of the MIPI C-PHY version 1.1. The signal $\textit{P}$$_{CPHY}$$\textit{[16:0]}$ is finally output with the clock signal $\textit{CLK}$$_{FRAME}$ for the source-synchronous clocking scheme.

III. CHIP IMPLEMENTATION AND MEASUREMENT RESULTS

Fig. 11. Implemented MIPI receiver bridge chip (a) photograph, (b) layout.

The proposed MIPI receiver bridge chip supporting the D-PHY version 2.0 and the C-PHY version 1.1 specifications was designed to be used in the FPGA-based frame grabber supporting the MIPI CSI-2 specification. It was fabricated using a 0.11-${\mathrm{\mu}}$m CMOS process with 1.2-V supply. Fig. 11 shows the chip photograph and layout of the implemented MIPI receiver bridge chip. The total chip size including pads is 3.15~mm ${\times}$ 3.15 mm. The low-profile quad flat package (LQFP) with 128 pins was used in the implemented MIPI receiver bridge chip. For the high-speed interface with camera modules, 10 pins are used by sharing the MIPI D-PHY interface pins for four data lanes and one clock and the MIPI C-PHY interface pins for three lanes. The LVCMOS interface between the MIPI receiver bridge chip and the FPGA is performed using 48 parallel data pins, six pins for three differential output clocks, three flag pins indicating the frame lock, and nine low power data pins. Other pins are used for the power supply and control signals. The power consumption for each operation of the MIPI D-PHY and C-PHY is approximately 157.5 mW and 265.8 mW, when the four data lanes and the three lanes for the MIPI D-PHY and CPHY are fully operated at data rates of 5.0 Gb/s/lane and 3 Gsymbol/s/lane, respectively.

Fig. 12. (a) Test environment for MIPI receiver bridge chip, (b) functional test of MIPI C-PHY receiver.

Fig. 12(a) shows the test environment to evaluate the implemented MIPI receiver bridge chip. The SV3C CPTX MIPI C-PHY Generator of Introspect Technology was used to supply the test patterns satisfying the MIPI D-PHY version 2.0 and C-PHY version 1.1 specifications to the implemented MIPI receiver bridge chip. The LVCMOS parallel output data, which is supplied to the FPGA in the frame grabber, are acquired by using external equipment such as a logic analyzer or a real time high-speed oscilloscope. In particular, because the implemented MIPI C-PHY receiver outputs the demapped result, its functional test was performed by using the mapper in the SV3C CPTX MIPI C-PHY Generator. Therefore, the function test the MIPI C-PHY receiver was achieved by comparing the 16-bit parallel input data of the SV3C CPTX MIPI C-PHY Generator and the 16-bit parallel output data of the implemented MIPI C-PHY receiver, as shown in Fig. 12(b).

Fig. 13. Measured eye diagrams of output of high-speed DPHY receiver at 5 Gb/s/lane (a) input signal, (b) w/o equalization, (c) w/ equalization.

Fig. 13 shows the measured eye diagrams of the output signal of the high-speed receiver for the MIPI D-PHY receiver according to the equalization of two amplifiers for the high-speed receiver. This measurement was performed in compliance with the MIPI D-PHY version 2.0 specification. Each lane is operated at a data rate of 5~Gb/s and the transmitted signal has the differential peak-to-peak amplitude of 340 mV. Furthermore, this measurement was performed using an additional test path bypassing the normal deserialization block. The eye diagram measured at the input node of the high-speed receiver had a smaller eye opening than the minimum eye opening of the MIPI D-PHY version 2.0 specification, as shown in Fig. 3(a). When the equalization for the high speed receiver is not performed, it is difficult to reliably receive the input data according to the result of the eye diagram shown in Fig. 13(b). Fig. 13(c) shows the eye diagram improved by using the equalization of the high-speed receiver. The measured eye diagram of the output of the high-speed receiver has the peak-to-peak time jitter of 77.5 ps, 0.39 unit interval (UI).

Fig. 14. Transmitted test pattern and deserilized parallel output data for MIPI D-PHY receiver at 5 Gb/s/lane (a) lane 1, (b) lane 2, (c) lane 3, (d) lane 4.

Fig. 14 shows the measurement results to verify the functional operations of the byte synchronization and deserialization for the MIPI D-PHY receiver. Due to the speed limitation of the logic analyzer, these results were acquired by using a real time high-speed oscilloscope for a data rate of 5 Gb/s/lane. The four data lanes were evaluated by receiving different test patterns including the seed signal $\textit{SEED[7:0]}$ for the byte synchronization and operated without bit errors at a data rate of 5 Gb/s/lane, as shown in Fig. 14(a)-(d). The seed signal of 8b’10111000, which is set for the MIPI D-PHY version 2.0 specification, was measured as a byte signal in four lanes.

Fig. 15. Measured eye diagram of received data and recovered clock at 2.56 Gsymbol/s/lane (a) input signal, (b) data w/o equalization, (c) data w/ equalization, (d) clock w/o equalization, (e) clock w/ equalization.

Fig. 16. Measured eye diagram at 3 Gsymbol/s/lane (a) received data, (b) recovered clock.

Fig. 15 shows the measured results to evaluate the performance of the high-speed receiver of the MIPI C-PHY receiver. This measurement was performed by supplying the high-speed signal with a data rate of 2.56 Gsymbol/s/lane and three voltage levels of 125 mV, 250~mV, and 375 mV generated by the external pattern generator through the FR4 printed circuit board 10-inch channel with connectors. Fig. 15(a) shows the eye diagram with channel insertion loss at the input node of the high-speed receiver. There is no time margin and voltage margin for stable data acquisition. The high-speed receiver, which uses three differential amplifiers reducing the effect on the variations of the input common-mode voltage, made the time margin large than 0.5 UI, as shown in Fig. 15(b). Furthermore, the equalization of the high-speed receiver additionally provided a 43 ps reduction of the peak-to-peak time jitter by compensating for insertion loss at a data rate of 2.56 Gsymbol/s/lane, as shown in Fig. 15(c). Fig. 15(d) and (e) show that the peak-to-peak time jitter of the recovered clock is reduced from 133.8 ps to 98.75 ps by using the equalization of the high-speed receiver. Fig. 16(a) and (b) are the measurement results of the received data and recovered clock at a data rate of 3 Gsymbol/s/lane that meets the MIPI C-PHY version 1.1 specification. The measured peak-to-peak time jitters of the received data and recovered clock are 128 ps and 115 ps, respectively.

Fig. 17. Test pattern supplied to test equipment and deserilized parallel output data for MIPI C-PHY at 3 Gsymbol/s/lane (a) lane 0, (b) lane 2, (c) lane 3.

The functional operations of the decoder, seed detector, deserializer, and demapper for the MIPI C-PHY receiver were verified by checking the measurement results shown in Fig. 17. This measurement was performed at a data rate of 3 Gsymbol/s/lane, and the functional operations of three data lanes were evaluated by using the test method shown in Fig. 12(b). The $\textit{CLK}$$_{LANE\#}$ is the output signal of the frame clock $\textit{CLK}$$_{FRAME}$ obtained by dividing the frequency of the recovered clock $\textit{CLKA}$ by 3.5 shown in Fig. 10. The frame lock signal $\textit{FLAG}$$_{LANE\#}$ and the 16-bit parallel LVCMOS data per lane $\textit{PO}$$_{LANE\#}$$\textit{[15:0]}$ were output synchronously on the falling edge of the frame clock $\textit{CLK}$$_{LANE\#}$. Then, the FPGA can sample these signals at the rising edge of $\textit{CLK}$$_{LANE\#}$. According to the MIPI C-PHY version 1.1 specification, the $\textit{SEED}$$_{FLIP}$$\textit{[6:0]}$, $\textit{SEED}$$_{ROTATE}$$\textit{[6:0]}$, and $\textit{SEED}$$_{POLARITY}$$\textit{[6:0]}$ for the frame lock are 7b’0111110, 7b’1000001, and 7b’1000001, respectively. In this work, the three seed data of 21 bits are converted to 0xC303 by the operation of the 21-to-16 demapper. Fig. 17 shows that each lane of the implemented MIPI C-PHY receiver normally receives the seed data of 0xC303 and thus activates the frame lock signal $\textit{FLAG}$$_{LANE\#}$. Furthermore, the measured 16-bit parallel data of all three lanes are confirmed without bit errors for each test pattern that is deserialized to the frame by the seed data.

The proposed receiver bridge chip has an improved data rate for longer channels compared to the previous study on the MIPI D-PHY bridge chip ⁽⁹⁾, as shown in Table 1. It also supports all functions including the clock recovery of the MIPI C-PHY version 1.1 specification to be used as a receiver bridge chip between the MIPI embedded chip and the FPGA chip.

IV. CONCLUSIONS

The MIPI receiver bridge chip supporting the D-PHY version 2.0 and C-PHY version 1.1 specifications was implemented on a single chip by using a 0.11-${\mathrm{\mu}}$m CMOS process with 1.2-V supply. The proposed MIPI receiver bridge chip provides a data rate of over 20 Gbps per chip for both the MIPI C-PHY with 3 lanes and D-PHY with 4 data lanes. It is used in the FGPA-based frame grabber supporting the MIPI CSI-2 specification. The area of the single chip is 3.15 mm ${\times}$ 3.15 mm. The power consumption of the MIPI D-PHY and C-PHY receivers is 157.5 mW and 265.8 mW, respectively. Both the MIPI D-PHY and C-PHY receivers perform the deserialization with byte synchronization for the low-speed interface with the FPGA. The high-speed receiver for the MIPI D-PHY receiver, which has the AC equalization using capacitor coupling in the common-gate level shifter and the DC equalization using source degeneration, improved the signal integrity of the SLVS data with a data rate of 5 Gb/s/lane. The high-speed receiver for the MIPI C-PHY receiver consists of three differential amplifiers to increase the bandwidth and voltage gain while reducing the effect on the variation of the input common-mode voltage. Furthermore, the clock recovery with deglitch circuit was proposed to generate the clock signal of 1.5~GHz from the received three data of 3 Gsymbol/s/lane.