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  1. (Department of Electrical and Computer Engineering and the Inter-university Semiconductor Research Center (ISRC), Seoul National University, Seoul 141-744, Korea. )
  2. (Flash Advanced Design Team, SK hynix Inc., Icheon-si, Gyeonggi-do, 17336, Korea )



3D NAND flash memory, natural local self boosting(NLSB), program disturbance, band-to-band tunneling(BTBT), hot carrier

I. INTRODUCTION

In order to distinguish between the selected string to be programmed and the unselected string not to be programmed during the program operation of the NAND flash memory, the high bit line voltage(V$_{\mathrm{BL}}$) is used to turn off the drain selection line(DSL) and source selection line(SSL) transistor to form the boosting channel potential (1,2).

In 2D NAND, all word lines(WLs) have the same boosting potential regardless of the programming cell(selected WL) and the pass cell(unselected WL) (3). Therefore, high electric field occurs at the both ends due to the large difference between the boosting WL channel potential and low channel potential of DSL or SSL, resulting in band-to-band tunneling(BTBT). Some electrons caused by BTBT unintentionally tunnel into the charge trap layer, resulting in the problem of V$_{\mathrm{th}}$ changing (4,5). This problem is called hot carrier injection(HCI).

In the case of 2D NAND, because HCI problem occurs only at the both ends, the problem can be solved by adding dummy WLs. However, in the inhibited string of 3D NAND, the channel potential of the programming cell naturally becomes higher than that of the pass cell (6). As a result, hot carrier injection of the programming cell can cause a serious V$_{\mathrm{th}}$ shift in 3D NAND. Also, based on the scaling trend of semiconductors, HCI can cause serious problems as the electric field in the lateral direction becomes stronger as the length of spacer, gate and the thickness of O/N/O decrease.

NAND HCI modeling had already been reported, but it is a 2D NAND-based modeling (7). We studied the channel potential and HCI phenomenon during the programming operation by the technology computer-aided design(TCAD) and developed the model for HCI in 3D NAND flash memory.

II. RESULTS

1. Natural Local Self Boosting(NLSB)

NLSB is a unique phenomenon of 3D NAND compared with 2D NAND. In 2D NAND, the soft programming problem in the inhibited string(unselected string) is a severe problem. Since the boosting potential is mainly determined by the pass voltage, the soft programming caused by Fowler-Nordheim(FN) tunneling of selected WL is problematic because the voltage difference between the program voltage and the boosting channel potential is quite large (3).

Fig. 1. (a) Electric potential contour in TCAD, (b) channel potential of the selected string and the unselected string.

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Fig. 1(a) and (b) show electric potential contour of the inhibited 3D NAND string in TCAD and the channel potential of the selected string to be programmed and unselected string not to be programmed. The programming cell(selected WL) has the higher channel potential than that of pass cells(unselected WLs) naturally in the 3D NAND due to the electron flow and the change of the state over time without using the local self-boosting method (6).

This phenomenon reduces the soft programming caused by FN tunneling of the programming cell in the inhibited string. However, due to NLSB, hot carrier injection can occur in the 3D NAND near the programming cell as well as at both ends where the DSL and SSL are located.

Fig. 2. (a) Bias scheme for program inhibited string, (b) energy band diagram of the inhibited string.

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2. Program Disturbance by Hot Carrier Injection

Fig. 2(a) and (b) show the inhibit bias scheme and assumed program-verify(PV) states for modeling and the energy band diagram. In Fig. 2(a), because the programming operates in page units, the only difference between selected string and unselected string is bit line voltage(V$_{\mathrm{BL}}$). And we define that the programmed and unselected WL above the selected WL is a neighboring cell of the programming cell.

Also, V$_{\mathrm{th}}$ of the programmed state is 3 V, V$_{\mathrm{th}}$ of the erased state is {--}2 V. And single programming pulse is used.

Since the PV state of the neighboring cell of the programming cell is dominant in generating maximum electric field at the direction of the channel, the following PV states are assumed.

As can be seen from the Fig. 2(b), the energy band near the programming cell due to NLSB is considerably curved and the tunneling distance between the valence band and the conduction band is considerably enough close to cause BTBT.

Due to BTBT, electron-hole pairs are generated, and some of the electrons, which have a large energy, tunnel into the charge trap layer near the programming cell and cause an unintentional V$_{\mathrm{th}}$ shift.

Fig. 3(a) shows the device that performed the simulation. Trapped electron charge (eTrapped charge) in nitride by HCI are located between the programmed state of the unselected WL and the erased state of the selected WL. Also, these electrons are seen to be located close to the tunneling oxide in the y-direction.

Fig. 3. (a) Trapped charge distribution by HCI in the simulation device, (b) electric field, (c) BTBT and trapped electron charge(eTrapped charge) in nitride by HCI at the same position of the simulation device.

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As can be seen in Fig. 3(b), the peak point of the electric field appears in the spacer region of the programming cell due to the voltage difference between the boosting potential of the programming cell and the boosting potential of pass cells. And its peak point is coincided with the peak point of BTBT.

On the other hand, in Fig. 3(c), the peak point of trapped electron charge in nitride by HCI is located in the direction of the programming cell rather than the peak of BTBT. It is because electrons generated by BTBT must obtain sufficient energy with the lateral electric field(x-direction) for being injected as hot carriers. When NLSB occurs, the trapped charges injected as hot carriers show a peak in the spacer region slightly distant from the gate of the programming cell. This differs from the injection by FN tunneling where trapped charges are located at the center of the gate of the programming cell.

Fig. 4. (a) Maximum lateral electric field, (b) V$_{\mathrm{th}}$ shift of the programming cell by HCI according to V$_{\mathrm{pgm}}$, V$_{\mathrm{pass}}$.

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The value of the maximum lateral electric field increases as the pass voltage is lower and the program voltage is higher. And V$_{\mathrm{th}}$ shift of the programming cell also has the same tendency as can be seen in Fig. 4. V$_{\mathrm{th}}$ shift due to hot carrier injection has been confirmed that there is depenency of the electric field. This suggests that the modeling of HCI should be based on accurate trends of the electric field.

3. Channel Potential Lowering

Fig. 5. Change of channel potential near programming cell according to time.

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Fig. 6. Maximum channel potential of programming cell in case of the w/ BTBT model and w/o BTBT model.

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The electrons generated by the BTBT are accumulated in the channel under the programming cell by the high program voltage. Over time, the electrons continue to gather and consequently lower the channel potential of the programming cell.

As shown in Fig. 5, the channel potential of the programming cell gradually decreases over time.

Fig. 6 shows that the maximum channel potential of the model with the BTBT is gradually lowered as electrons accumulate continuously during the duration time of programming pulse after rising time, whereas that of the model without BTBT maintains constant.

This programming cell channel potential lowering should be considered to describe HCI exactly.

4. Modeling

Because the hot carrier injection is strongly dependent on the electric field, the channel potential is used to describe the exact electric field. Finally, a new HCI current modeling based on channel potential in the programming operation of 3D NAND has been developed as follows.

(1)
$$ \mathrm{V}_{\mathrm{pgm}(\mathrm{ch})}=V_{p a s s}+\gamma\left(V_{p g n}-V_{p a s}\right)-\frac{1}{C_{c h}} \int I_{b t b t} d t $$

(2)
$$ \mathrm{V}_{\mathrm{pass}(\mathrm{ch})}=V_{p a s s} $$

(3)
$$ \mathrm{E}_{1}=\frac{V_{P g m(c h)}-V_{p a s s(c h)}+V_{P V(c h), 2 P-E}}{A \times t_{s p a c c r}} $$

(4)
$$ \mathrm{E}_{\mathrm{ox}}=\frac{C_{r}\left(V_{p g n}-V_{p g m(c h)}+V_{p V(c h), E}\right)}{t_{o x}} $$

(5)
$$ \mathrm{I}_{\mathrm{btt}}=B \times E_{l} \times\left(V_{p g m(c h)}-V_{p a s s(c h)}+V_{P V(c h), P-E}\right) \times \exp \left(-\frac{C}{E_{l}}\right) $$

(6)
$$ \mathrm{I}_{\mathrm{HCI}}=D \times I_{b t t t} \times \exp \left\{-\frac{\left(3.1-\alpha E_{\alpha x}^{\frac{1}{2}}-\beta E_{\alpha x}^{\frac{2}{3}}\right)}{\lambda E_{l}}\right\} $$

V$_{\mathrm{pgm(ch)}}$, V$_{\mathrm{pass(ch)}}$ mean the channel potential of the programming cell and pass cell respectively. And V$_{\mathrm{pv(ch)}}$ is the term to express that the PV states of the programming cell and the neighboring cell affect the channel potential.

The first and second term of Eq. (1) are the terms to express NLSB, and the third term is the expression of lowering by accumulated electrons generated by BTBT. Also, Eq. (2) have been confirmed that when NLSB occurs, the channel potential of the pass cell coincided with V$_{\mathrm{pass}}$ by TCAD. C$_{\mathrm{ch}}$ means the capacitance of channel.

Eqs. (3, 4) are the maximum lateral electric field and the maximum oxide electric field respectively expressed by channel potential. The change of channel potential due to the programmed state of the neighboring cell of the selected WL and the erased state of the selected WL is expressed as V$_{\mathrm{pv(ch),P-E}}$ in the numerator term of the lateral electric field. In the maximum oxide electric field, we added V$_{\mathrm{pv(ch),E}}$ which means channel potential change by erased state of selected WL. C$_{\mathrm{r}}$ means the capacitance coupling ratio of O/N/O. Also, t$_{\mathrm{spacer}}$, t$_{\mathrm{ox}}$ are the length of the spacer and the thickness of the tunneling oxide respectively.

Fig. 7. (a) Max Elateral, (b) Max Eox, (c) BTBT current, (d) HCI current fitting results of simulation data and modeling.

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Eq. (5), BTBT current for 3D NAND flash memory, is represented through modifying the well-known BTBT current modeling of the PN junction (8).

Eq. (6), HCI current is based on the lucky electron model, and the SPICE-friendly NAND HCI model (7,9). Through TCAD, it has been confirmed that HCI occurs more frequently when more BTBT occur, and it has been considered. Also, as the mean free path becomes longer, the electrons become less scattering and the probability of obtaining energy increases. And when the lateral electric field becomes stronger, the probability of electrons getting energy increases. These have been considered by putting into the denominator term of exponential term. Besides, when the electric field of the tunneling oxide becomes stronger, the electrons in the channel feel lower energy barrier than 3.1 eV that is the original energy barrier between silicon and oxide. This has been also considered by putting into the numerator term of exponential term. Finally, through iteration of Eqs. (1-5), HCI current is calculated numerically.

$\gamma, \alpha, \beta, \lambda$ are model parameters. ${\gamma}$ is 0.7 as mentioned in (6). ${\alpha}$, ${\beta}$, ${\lambda}$ are parameters based on the lucky electron model. ${\alpha}$ is 2.6$\times $10$^{-4}$ [(V${\cdot}$cm)$^{\mathrm{1/2}}$], ${\beta}$ is 3.0$\times $10$^{-5}$ [(V${\cdot}$cm$^{2}$)$^{\mathrm{2/3}}$], ${\lambda}$ is 8.9$\times $10$^{-7}$ [cm]. A, B, C, D are fitting parameters.

Fig. 7(a)-(d) show fitting results of the extracted data by TCAD when V$_{\mathrm{pass}}$ = X+2, V$_{\mathrm{pgm}}$ = Y+2 and modeling. Modeling successfully describes HCI current according to the programming time.

III. CONCLUSION

We analyzed channel potential and HCI in the inhibited string in programming operation of 3D NAND flash memory. As a result, electrons and holes generated by BTBT not only cause the change of the channel potential, but also result in the unintentional Vth shift of the programming cell due to HCI. The tendency of HCI follows the trend of electric fields, and as a result, the higher the program voltage, the lower the pass voltage, the higher HCI occurs. Finally, we developed HCI modeling with BTBT. The proposed modeling shows the exact change of channel potential and electric field versus time. Based on the exact electric field modeling, hot carrier injection current modeling over time was completed and fitted well with the simulation data.

ACKNOWLEDGMENTS

This paper was result of the research project supported by SK Hynix Inc. and the authors would like to thank Synopsys providing TCAD tool.

REFERENCES

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Oh Dongyean, 2007, A new self-boosting phenomenon by source/drain depletion cut-off in NAND flash memory., 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop. IEEEDOI
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Choi Jeong-Hyuk, Shin Yun-sung, 9 Dec 2003, ,Method of programming NAND-type flash memory., U.S. Patent, No. 6,661,707Google Search
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Author

Yongmin Lee
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Yongmin Lee received the B.S. degree in Electrical and Computer Engineering from Seoul National University(SNU) in 2018.

He is currently pursuing the M.S. degree with the Department of Electrical and Computer Engineering, Seoul National University(SNU), Seoul, Korea.

Sungbak Kim
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Sungbak Kim received B.S. and M.S. degree in electronic engineering from Chungbuk National University, Cheongju, Korea, in 1998 and 2000.

He is currently working at Flash Advanced Design Team in SK hynix.

Hyungcheol Shin
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Hyungcheol Shin received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1985 and 1987, respectively, and the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1993. From 1994 to 1996, he worked as a Senior Device Engineer in Motorola. From 1996 to 2003, he was with the Department of Electrical Engineering and Computer Sciences at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, as an Associate Professor.

From 2001 to 2002, he worked as a Staff Scientist in Qualcomm. Since 2003, he has been with Seoul National University(SNU), Seoul, Korea, where he is currently a professor in the school of Electrical Engineering and Computer Science. From 2012 to 2013, he was a Director of the Inter university Semiconductor Research (ISRC).