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1. (Graduate School of IT Convergence Engineering, Gachon University, Seongnam-si, Gyeonggi-do 13120, Korea)
2. (Department of Electronics Engineering, Gachon University, Seongnamsi, Gyeonggi-do 13120, Korea)

DC compact model, TFET, devicecircuit co-optimization, device simulation, circuit simulation, HSPICE, circuit design

## I. INTRODUCTION

##### (2)
$$f_{l}(E)=\frac{1}{1+\exp \left[\left(E-E_{F l}\right) / k T\right]}$$

##### (3)
$$f_{r}(E)=\frac{1}{1+\exp \left[\left(E-E_{F r}\right) / k T\right]}$$

##### (15)
$$F_{V_{\mathrm{DS}}}=B_{0}\left(V_{\mathrm{GS}}\right) \cdot \exp \left[-\frac{V_{\mathrm{DS}}}{T\left(V_{\mathrm{GS}}\right)}\right]+B_{1}\left(V_{\mathrm{GS}}\right)$$

##### (16)
$$B_{0}\left(V_{\mathrm{GS}}\right)=\left(-3.64 \times 10^{4}\right) \exp \left(\frac{V_{\mathrm{GS}}}{0.43}\right)+\left(5.31 \times 10^{4}\right)$$

##### (19)
$$V_{a}=U \exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{th}}}{U}\right)$$

##### (20)
$$U=\gamma_{0} U_{0}+\left(1-\gamma_{0}\right) U_{0} \cdot\left(\frac{V_{\mathrm{GS}}-\gamma_{1}}{V_{\mathrm{th}}-\gamma_{1}}\right)$$

### 4. Ambipolar Current Modeling

##### (28)
$$F_{V_{\mathrm{DS}}}=B_{0}\left(V_{\mathrm{GS}}\right) \cdot V_{\mathrm{DS}}+B_{1}\left(V_{\mathrm{GS}}\right)$$

##### (29)
$$B_{0}\left(V_{\mathrm{GS}}\right)=\left(5.58 \times 10^{5}\right) \exp \left(\frac{V_{\mathrm{GS}}}{0.58}\right)+\left(9.39 \times 10^{5}\right)$$

##### (30)
$$B_{1}\left(V_{\mathrm{GS}}\right)=\left(1.05 \times 10^{5}\right) \exp \left(\frac{V_{\mathrm{GS}}}{0.27}\right)+\left(1.68 \times 10^{4}\right)$$

The current density as a function of both $\textit{V}$$_{\mathrm{GS}} and \textit{V}$$_{\mathrm{DS}}$ can be expressed back in the same form in Eq.(10).

## IV. RESULTS AND DISCUSSION

Fig. 8. Transfer characteristics obtained in the HSPICE simulation with the developed TFET compact model having higher completeness with the ambipolar current modeling results.

Figs.7(a) and (b) demonstrate the transfer and the output curves of the designed TFET, in comparison between the results from the TCAD device simulation and the modeling.

The reference in comparison has been obtained by the TCAD device simulation results from the TFET device based on the SOI platform. The modeling results in Figs.7(a) and (b) have been obtained by the SPICE simulation. For obtaining the circuit simulation results, the compact models have been prepared first by coding the corrected mathematical equations and functions in III. 1 through 3 by Verilog-A, and then, transferred into HSPICE [30,31]. The curves plotted in Figs.7(a) and (b) are the results after performing the correction in $\textit{f}$ as a function of $\textit{V}$$_{\mathrm{GS}} and \textit{V}$$_{\mathrm{DS}}$.

Fig.8shows the transfer curves of the TFET obtained from the HSPICE simulation results, at $\textit{V}$$_{\mathrm{DS}} = 0.9 V and 1 V. \textit{V}$$_{\mathrm{DD}}$ in Eqs.(24) and (25) is assumed to be 1 V and it is confirmed by the figure that the transfer curve in the negative $\textit{V}$$_{\mathrm{GS}} region is shifted leftward for smaller positive \textit{V}$$_{\mathrm{DS}}$ as can be predicted by Eqs.(24) and (25). In the HSPICE simulation, the off-state current has been set to a constant, 1.65${\times}$10$^{-16}$ A/μm, which is transplanted from the TCAD device simulation results. It has been successfully demonstrated that the developed TFET compact model provides a good agreement between the current characteristics by TCAD device simulation and HSPICE circuit simulation results: ambipolar and on-state currents in the transfer curves and the on-set voltages and saturation currents in the output curves under various bias conditions.

## V. CONCLUSIONS

In this work, a more accurate DC compact model for an SOI TFET has been developed. The master equation has been more refined with coefficient functions of higher accuracy. Verilog-A coding and running the compact model at an HSPICE have confirmed the high accuracy of the developed model in comparison with the raw data, the TCAD physical device simulation results. The accuracies have been found in both transfer and output characteristics. In particular, the ambipolar current characteristics have been considered in this work for higher practicability and reality in more complicated circuit designs where even a tiny amount of power consumption should be considered.

### ACKNOWLEDGMENTS

This work was supported by the National Research Foundation of Korea (NRF) funded by the Korean Ministry of Science and ICT (MSIT) through a Mid- Career Researcher Program (NRF-2017R1A2B2011570) and also supported by the Gachon University Research Fund of 2019 (GCU-2019-0324).

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## Author

##### Seoyeon Go

Seoyeon Go received the B.S. in electronics engineering from Gachon University, Seongnam, Korea, in 2019, and had been pursuing the M.S. degree.

Her research interests include optimal design of device CMOS devices for high-speed low-power applications, device-circuit mixed-mode simulation, compact modeling of novel devices for circuit design by HSPICE.

She is a Student Member of IEIE.

##### Won Jae Lee

Won Jae Lee received the B.S. degree in electrical engineering and the M.S. degree in electrical material engineering from Kwangwoon University, Seoul, Korea, in 1980 and 1982, respectively, and received the Ph.D. degree in electrical engineering from Hongik University, Seoul, Korea, in 1988.

He worked as a Postdoctoral Researcher at Tokyo Institute of Technology (TIT), Japan, from 1993 to 1994.

Also, he worked as an Exchange Researcher at Northwestern University, IL, USA, in 2009. Currently, he is a Professor at the Department of Electronics Engineering, Gachon University, Korea.

His research interests include photovoltaic device, organic light-emitting diode (OLED), and organic thin-film transistor (OTFT).

##### Seongjae Cho

Seongjae Cho received the B.S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2004 and 2010, respectively.

He worked as an Exchange Researcher at the National Institute of Advanced Industrial Science and Technology (AIST) in Tsukuba, Japan, in 2009.

Also, he worked as a Postdotoral Researcher at Seoul National University in 2010 and at Stanford University, CA, USA, from 2010 to 2013.

Currently, he is working as an Associate Professor at the Department of Electronics Engineering, Gachon University, Korea.

His research interests include emerging memory technologies, nanoscale CMOS devices, group-IV optical devices, and hardware-driven neuromorphic devices and systems.

He is a Life Member of the IEIE.