I. INTRODUCTION
In modern wireless and wired broadband communication, the demand of high-speed, low-resolution
DAC is increased for high energy-efficient signal processing [1-4]. For example, the Ultra-Wideband (UWB) technology requires a Digital-to-Analog Converter
(DAC) with accuracy above 4 bit (preferably 6 bit for design margin) and operating
speed beyond 1 GS/s [5]. Multiband Orthogonal Frequency-division Multiplexing (MB-OFDM) and Direct Spectrum
Code Division Multi Access (DS-CDMA) technologies are widely used in UWB. In the MB-OFDM
approach, the spectrum from 3.1 to 10 GHz is divided into 14 channels with each channel
width of 528 MHz [6]. So, the sampling rate should be larger than 1.056 GS/s.
In this paper, a 2 GS/s, 6-bit DAC in a SMIC 0.18 μm CMOS technology is designed and
presented considering the trade-off between power consumption and the sampling rate.
To realize larger linear range and fast switching, the source degeneration switch
is designed instead of the traditional differential switch. PMOS cascode circuits
are used as the current sources to improve their performance and a clock drive circuit
which has good drive ability and low jitter is designed and presented. The rest of
the paper is organized as follows. In section Ⅱ, the DAC structure and key building
blocks as the current source array, the switch array and the clock drive circuit will
be analyzed. Section Ⅲ presents the measurement setup and measurement results of the
DAC. Conclusions will be drawn in Section Ⅳ.
II. DAC STRUCTURE AND KEY BUILDING BLOCKS
1. The System Structure for the DAC
Among various DAC topologies, current steering (CS) DAC is the best candidate for
high speed applications because it drives resistive load directly without an output
buffer. CS DACs are based on an array of matched current sources that are switched
to the output. Three different architectures are possible depending on the implementation
of this array: binary, unary and segmented. The binary structure is simple and easy
to implement, but it has serious glitch, poor linearity, and cannot achieve high resolution.
The unary structure requires an additional decoding circuit to convert the input binary
code into a thermometer code, and also requires large number of current sources, and
its scale increases exponentially with resolution. However, its linearity and monotonicity
are good, and the glitch of the output signal will be greatly weakened, also the requirement
of the process matching is lower. The segmented structure can balance the performance
and the cost. In this design it can be 5+1, 4+2, 3+3, 2+4, 1+5. No matter what combination
form, the Integral Nonlinearity (INL) errors are the same [7], the Differential Nonlinearity (DNL) error in the segmented architecture can be presented
as Eq.(1) with binary-weighted bits (B) and the relative standard deviation of a unit current
source ($\sigma(I) / I$).
According to Eq.(1), for the combination form of 5+1, 4+2, 3+3, 2+4, 1+5 the DNL and current numbers
are 1.73$\sigma(I) / I$ and 32 signals, 2.64$\sigma(I) / I$ and 17 signals, 3.87$\sigma(I)
/ I$ and 10 signals, 5.56$\sigma(I) / I$ and 7 signals, 7.94$\sigma(I) / I$ and 6
signals. In this design, to balance performance and complexity, and the DNL performance
is taken seriously so finally 4+2 is selected, in which the high 4 bits take the thermometer
code while the low 2~bits take the binary code. The block diagram of the system is
shown in Fig. 1. Among them, D0\textasciitilde{}D5 are the input digital codes, $\textit{V}$$_{\mathrm{o}}$
and $\textit{V}$$_{\mathrm{on}}$ are output differential analog signals.
Fig. 1. ystem structure of the DAC.
The digital part are labelled green in Fig. 1, which includes the input register, the thermometer decoding circuit, the synchronous
latch, the switch array and the clock driver circuit. The 6-bit input digital signals
are synchronized into the input register under the control of the clock. Through the
decoding circuit, the output data are sent to the synchronous latches. Through the
processing of the synchronous latch circuit, the timing synchronization and the low
crossing point signal are produced, which can be used to control the switch array
to select different current sources. The analog part are labelled yellow in Fig. 1, which includes bandgap voltage reference, voltage to current converter and current
source array. The bandgap circuit provides an accurate reference voltage, and then
the voltage to current conversion circuit converts the reference voltage into a reference
current, and the reference current provides a bias to the entire current source through
a cascode current mirror to bias the circuit. The design of the key building blocks
will be analyzed from the performance perspective.
2. The Current Source Array
Current source array is the most important element in ultra-high speed DAC, and its
performance directly affects the static and dynamic performance of the whole DAC system.
On top of Fig. 1 is the current source array of the DAC. The design requirements for the current source
are: good matching between the current sources and large output impedance.
For the current source, the transistor works in the saturation region, and the current
can be expressed as
In Eq.(2), ${\beta}$ is the transconductance parameter, ${μ}$ is the carrier mobility of MOS
transistors, $\textit{C}$$_{\mathrm{ox}}$ is the gate oxide capacitance per unit area.
W and L are the width and length of the MOS transistor, $\textit{V}$$_{\mathrm{GS}}$
is the gate-source voltage and $\textit{V}$$_{\mathrm{TH}}$ is the threshold voltage.
The current deviation can be expressed as
As ${\beta}$ and $\textit{V}$$_{\mathrm{TH}}$ are independent random variable, the
matching characteristics of MOS transistors can be expressed by the variance of current,
Here, for convenience of discussion, two parameters of variance are derived.
$\textit{A}$$_{\mathrm{{β}}}$ and $\textit{A}$$_{\mathrm{VTH}}$ are the mismatch parameters
of current source for ${\beta}$ and $\textit{V}$$_{\mathrm{TH}}$, respectively.
From Eq. (4-6) we can get
For the matching requirement, a thermometer code n-bit DAC array generally consists
of N=2$^{\mathrm{n}}$ identically designed unit current sources, one of them is the
dummy, The k$^{\mathrm{th}}$ current can be written as
In the above equations, ${\varepsilon}$$_{\mathrm{k}}$ stands for the error between
the k$^{\mathrm{th}}$ current value and the mean value of the current source. $\overline{I}$
is the mean value of the output current. The relation between DAC static performance
(DNL, INL) and current source error [8] is listed in Eq. (9, 10).
Here X is the digital input code (0{\textless}X{\textless}N). The influence of current
source matching error on the SFDR of CS DAC is analyzed [9] based on the power spectrum analysis of the current source random matching error,
which can be presented in Eq.(11).
${\sigma}$$_{\mathrm{u}}$ is the matching error between the identically designed unit
current sources. It can be seen from Eq. (9-11) that the random matching error of the current source directly affects the static
and dynamic performance of the CS DAC.
Among the three static indicators of DNL, INL and INL yield, INL yield has the highest
requirement for current source mismatch. According to Bosch Model [10], the relation between INL Yield and relative deviation can be expressed as
Here, C can be written as
$\mathrm{inv}\_ \text{norm}_{(- x,x)}$ is the inverse function of the normal cumulative
function.
Setting the 10 bit accuracy, for INL_Yield equal to 99.7%, the $σI$/I value should
be smaller than 0.5%, the mismatch characteristics of MOS transistors are analyzed
and deduced according to Eq.(7), and the minimum area of the unit current source needs to be satisfied with Eq.(14):
The minimum area of the unit current source transistor is 16.9 $μm^2$ according to
Eq.(14). In this design, the W and L are set to be 18 μm and 1.5 μm.
For the output impedance requirements, we can obtain the influence of current source
impedance on the static and dynamic performance of DAC respectively [11].
For the static performance,
Here i represent the value of the ith current source, $\rho=R_{\mathrm{L}} / r_{0}$,
the load resistance is expressed as $\textit{R}$$_{\mathrm{L}}$, and $\textit{r}$$_{0}$
stands for the output impedance of the unity current source. The influence of output
impedance on dynamic performance [12] can be obtained in Eq.(17).
From Eq.(17) it can be seen that the SFDR of CS DAC can be improved with the increase of unit
current source output impedance while other conditions remain unchanged.
Based on the above analysis, set $\textit{R}$$_{\mathrm{L}}$ equal to 50 ${ω}$ for
matching purpose, and if we want the SFDR better than 50 dB, the output resistance
should be larger than 15 K${ω}$, here a PMOS cascode circuit is designed, as shown
in Fig. 2.
Fig. 2. The current source designed.
To ensure good matching performance between the current sources and reduce their area,
the M1 transistor should be allocated larger overdrive voltage, M2 as the common gate
transistor can improve the output impedance of the whole current source. PMOS is chosen
to implement the current source for three reasons. 1. The PMOS transistor has a smaller
leakage current mismatch compared with its NMOS counterpart; 2.The PMOS transistor
is independently produced in the N-well and can effectively isolate the crosstalk
and other noise through the substrate; 3.The mobility of the hole is lower than the
electron, and the PMOS current source has a lower 1/f noise relative to the NMOS transistors
[13]. In addition, M2 also plays an isolation role, which can significantly reduce the
influence of S point voltage change on the value the current source.
3. The Switch Array
Attentions has to be paid to the following design considerations of the current switch:
switch control signal should be synchronized; differential switch cannot turn off
at the same time, always ensure the “make before break”; switch on resistance should
be as small as possible; switch charge injection and clock feed through effect should
be as small as possible; switch source node voltage fluctuation should be small.
According to the requirements of the above analysis, the source degeneration switch
is designed in this paper, and the specific circuit is shown in Fig. 3(b). Compared with the traditional differential switch, shown in Fig. 3(a), two normally on dummy transistors are connected at the source end to isolate the
source and the output of the current, so that the coupling of the control signal will
not affect the S point, nor will the bias point be affected. The switch structure
can not only increase the input voltage range of the two switch linear transmission,
but also reduce the capacitance of the gate input, thereby reducing the glitch at
the output, and improve the dynamic performance of the CS DAC.
For the traditional differential switch, shown in Fig. 3(a), ignoring the subthreshold conducting, if the differential voltage (${δ}$$\textit{V}$$_{\mathrm{in}}$=$\textit{V}$$_{\mathrm{s}}$-$\textit{V}$$_{\mathrm{sn}}$)
is larger than $\textit{V}$$_{\mathrm{min1}}$, one transistor is cut off, and all
the current $\textit{I}$$_{\mathrm{cs}}$ goes through the other transistor, $\textit{V}$$_{\mathrm{min1}}$can
be expressed in Eq.(18)
Fig. 3. The switch array.
For the source degradation switch designed, the voltage $\textit{V}$$_{\mathrm{min2}}$
can be expressed in Eq.(19)
Here, $\textit{g}$$_{\mathrm{m }}$is the transconductance of switch transistor (M3,
M4 & M9, M10), $\textit{R}$$_{\mathrm{on}}$ stands for the equivalent resistance of
degeneration transistor (M7, M8). It is obvious that the source degeneration switch
has larger linear range.
For the traditional differential switch, if ${δ}$$\textit{V}$$_{\mathrm{in}}${\textless}{\textbar}$\textit{V}$$_{\mathrm{min1}}${\textbar},
the input capacitance seen from the gate of switch PMOS transistor can be expressed
in Eq.(20)
However, for the source degradation switch designed, this value is presented in Eq.(21)
It can be seen that the input capacitance is greatly reduced, so that the clock can
work at higher speed.
Fig. 4 compares the DC and transient characteristic of source degeneration switches with
the traditional ones by simulation.
Fig. 4. Comparison of source degeneration switches with the traditional ones.
Fig. 4(a) shows the DC characteristics, curve 1 is the traditional switch, curve 2 is the source
degradation switch. It can be seen that the linear range for the source degeneration
switch is significantly greater than the traditional differential switch. The source
degeneration switch designed can realize fast switching, thus improving its performance.
From the transient characteristic simulation in Fig. 4(b), it can be seen that the source degradation switch (curve 2) has a smaller glitch
output than the traditional differential switch (curve 1).
4. The Clock Drive Circuit
The clock synchronization performance and its drive capability will have a great impact
on the dynamic performance of CS DAC. Due to the transistors’ gate capacitance and
interconnect capacitance, the clock has to drive a large capacitive workload. In addition,
the input registers, decoding registers and the synchronization latch after the decoding
circuit has certain delay, thus the clock signal which controls the corresponding
flip flops and latches must have an equal or larger delay, to ensure the correctness
of data conversion. The clock driver circuit designed in this paper is shown in Fig. 5.
Fig. 5. Schematic diagram of clock tree drive circuit.
Fig. 6. The clock eye diagram of 2 GHz.
As shown in the diagram, the circuit uses the inverter chain structure to produce
the clock signals required by each branch of the inverter. The switch K1 and K2 are
used to ensure that the delay of the differential clock signals is consistent. The
external high-speed clock signal comes into the circuit, buffered by the inverter
and become two differential clock signals (n1 and n3, n2 and n4) which control the
trigger for input register; after a certain delay, produce the two differential clock
signal (n5 and n7, n6 and n8), which control the trigger for Flip-Flops of decoder
outputs; single-phase clock signal (n9, n10, n11) control the synchronization latch
to work. In the clock drive circuit, in order to enhance the driving ability of the
clock, the size of the inverter is increased step by step. To obtain the best time
delay and drive capacity, the size of each level should be exponentially the size
of its front stage.
Fig. 7. Die micrograph of the DAC.
Fig. 8. Demo board for DAC measurement.
The clock jitter has a very important influence on the performance of ultra-high speed
DAC, The simulated eye diagram for input signal of 2 GHz is shown in Fig. 6. The signal to noise ratio (SNR) limited by jitter [14] is presented in Eq.(22)
where $\textit{f}$$_{\mathrm{sig}}$ is the frequency of a sinusoidal input signal
and ${\sigma}$$_{\mathrm{t}}$ is the standard deviation of the sampling clock jitter.
For 1 GHz input, if we want the SNR performance better than 4 bit, then the clock
jitter should be less than 8.12 ps. It can be seen that the clock jitter of the circuit
is 3.92 ps, which meets the design requirements.
III. MEASUREMENT RESULTS
The DAC is designed and taped out in SMIC 0.18 μm CMOS technology. Fig. 7 is the Die micrograph and Fig. 8 is the photo of Demo board for DAC measurement.
Fig. 9. Measurement Setup.
Fig. 10. Measurement results of the static performance.
Measurement setup for this DAC is shown in Fig. 9.
A. Static Performance of The DAC
For the static performance measurement, the digital symbol is generated by the FPGA
board, and the input digital signal is increased from 000000 to 111111. The oscilloscope
is used to capture the output waveform. Then import the test data into the Matlab
and calculate the DNL and INL, and get the corresponding curves as shown in Fig. 10. It can be seen from the diagram that DNL is 0.11 LSB, INL is 0.25 LSB for the DAC
designed, which shows good linearity.
B. Dynamic Performance of The DAC
For the dynamic performance measurement, the digital symbol generated by the FPGA
board is put into the 6 bit DAC chip to be measured. The time domain and frequency
domain waves are observed by the oscilloscope and the spectrum analyzer. The performances
are presented below.
For input signal of 6MHz@2GSps, the frequency spectrum is presented in Fig. 11. As can be seen from the diagram, the SFDR is 51 dB.
Fig. 11. Dynamic measurement results for 6MHz@2GSps.
For input signal of 994MHz@2GSps, the frequency spectrum is presented in Fig. 12. As can be seen from the diagram, the SFDR is 32.4 dB.
Fig. 12. Dynamic measurement results for 994MHz@2GSps.
The SFDR performance as a function of signal frequency at conversion rates of 2 GSps
are summarized in Fig. 13.
Fig. 13. Measured SFDR for input signal frequency @2GSps.
The power consumption of the DAC for 2 GSps sampling rate is 79 mW under a supply
voltage of 1.8 Volts. Among them 17.8 mW comes from the analog part and 61.2 mW from
the digital part. The performance summary of the DAC designed and a comparison with
the relevant literature published are listed in Table 1.
Table 1. DAC performance summary and comparison
|
Comparison
|
[1] JSSC'08
|
[15] TVLSI'15
|
[16] TVLSI'16
|
[17] JSTS'12
|
This work
|
|
Technology
|
0.13 mm CMOS
|
28 nm CMOS
|
90 nm CMOS
|
90 nm CMOS
|
0.18 mm CMOS
|
|
Resolution(bit)
|
6
|
6
|
6
|
6
|
6
|
|
Sampling Freq(GHz)
|
3
|
3.5
|
3.1
|
3.3
|
2
|
|
DNL(LSB)
|
NA
|
0.03
|
0.06
|
0.22
|
0.11
|
|
INL(LSB)
|
0.02
|
0.03
|
0.09
|
0.25
|
0.25
|
|
SFDR(dB)
|
47.3(30 MHz)
36.2(1.426 GHz)
|
46.4(600 MHz)
30.6(1.74 G)
|
47(48 MHz)
37.2(1.5 GHz)
|
47(16 M)
36.4(1.59 GHz)
|
51 (6 MHz)
32.4 (994 MHz)
|
|
Voltage(V)
|
1.2
|
1
|
1.2/1
|
1.2/1
|
1.8
|
|
Power(mW)
|
29
|
53
|
17.7
|
47
|
79
|
|
Core chip Area($mm^2$)
|
0.2
|
0.035
|
0.038
|
0.055
|
0.6
|
|
FOM(pJ)
|
0.15
|
0.24
|
0.09
|
0.22
|
0.61
|
IV. CONCLUSIONS
Based on SMIC 0.18 μm 1P6M CMOS technology, a 6 bit 2 GSps DAC is designed under 1.8
V supply voltage with the 4+2 segmented decoding current steering structure. The chip
area is 975 μm×775 μm. Wafer bonding measurement results show that DNL is 0.11LSB,
INL is 0.25 LSB. Under a sampling frequency of 2 GHz, SFDR is 51 dB for input signal
of 6 MHz and 32.4 dB for Nyquist input. The power consumption is 79mW. The 6 bit DAC
can work well under a sampling frequency of 2 GHz and is suitable for UWB applications
and other communication systems.
ACKNOWLEDGMENTS
The research is supported by National Natural Science Found (No. 61804081, 61828401),
China Postdoctoral Science Foundation (No. 2018M642292), Open project of State Key
Laboratory of Millimeter Waves (No. K201727), Open project of National and Local Joint
Engineering Laboratory of RF Integration and Micro-assembly Technology (No. KFJJ20170203)
and Scien-tific Research Foundation of Nanjing University of Posts and Telecommunications
(NUPTSF No. NY215138).
REFERENCES
Wu X., Palmers P., Steyaert M. S. J., 2008, A 130nm CMOS 6bit full Nyquist 3GS/s DAC,
IEEE Journal of Solid-State Circuits, Vol. 43, pp. 2396-2408
Greshishchev Y.M., Pollex D., Wang S.C., Besson M., Flemeke P., Szilagyi S., Aguirre
J., Falt C., Hamida N.B., Gibbins R., Schvan P., 2011, A 56GS/s 6b DAC in 65nm CMOS
with 256x6b memory, 2011 IEEE International Solid-State Circuits Conference, pp. 194-196
Nagatani M., Nosaka H., Sano K., Murata K., Kurishima K., Ida M., 2011, A 60-GS/s
6bit DAC in 0.5mm InP HBT Technology for optical communication systems, 2011 IEEE
Compound Semiconductor Integrated Circuit Symposium
(CSICS), pp. 1-4
Kwon Y. G., Lee S. H., Jeon Y. D., Kwon J. K., 2010, A 6b 1.4GS/s 11.9mW 0.11mm2 65nm
CMOS DAC with a 2-D INL bounded switching scheme, 2010 International SoC Design Conference,
pp. 198-200
Chen R. L., Chang S. J., 2012, A 6-bit Current-Steering DAC With Compound Current
Cells for Both Communication and Rail-to-Rail Voltage-Source Applications, IEEE Transactions
on Circuit And Systems—II: Express Briefs, Vol. 59, pp. 746-750
Chen R. L., Chang S. J., 2009, A 5-bit 1.35-GSPS DAC for UWB Transceivers, 2009 IEEE
International Conference on Ubiquitous Wireless Broadband, pp. 175-179
Bosch A. V., Borremans M. A. F., Steyaert M. S. J., Sansen W., 2001, A 10-bit 1-GSample/s
Nyquist current-steering CMOS D/A converter, IEEE Journal of Solid-State Circuits,
Vol. 36, pp. 315-324
Cong Y., Geiger R. L., 2002, Formulation of INL and DNL yield estimate on incurrent-steering
D/A converter, 2002 IEEE International Symposium on Circuits and Systems. Proceedings,
Vol. 3, pp. 149-152
Wikner J. J., Tan N., 1999, Modeling of CMOS Digital-to-Analog Converters for Telecommunication,
IEEE transactions on circuits and systems-II: Analog and Digital Signal Processing,
Vol. 46, pp. 489-499
Bosch A. V., Steyaert M. S. J., Sansen W., 2000, An accurate statistical yield model
for CMOS current-steering D/A converters, 2000 IEEE International Symposium on Circuits
and Systems. Emerging Technologies for the 21st Century. Proceedings, Vol. 4, pp.
105-108
Seo D., 2007, A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband
Wireless Transmitter, IEEE Journal of Solid-State Circuits, Vol. 42, pp. 486-495
Doris K., Roermund A. H. M., 2006, Wide-bandwidth high dynamic range D/A converters,
Springer, Boston, MA
Razavi B., Chen G., Cheng J., Zhang R., 2002.12, Design of Analog CMOS Intergrated
Circuits, Xian Jiaotong University Press, Xian, China, pp. 177
Zhang Q., Jiang Y., Wan S., Li P., Zhang T., 2016, An integrated low jitter PLL for
high speed high resolution DACs, 2016 International Conference on Integrated Circuits
and Microsystems (ICICM), pp. 172-175
Radulov G. I., Quinn P. J., Roermund A. H. M., 2015, A 28-nm CMOS 1 V 3.5 GS/s 6-bit
DAC With Signal-Independent Delta-I Noise DfT Scheme, IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, Vol. 23, pp. 44-53
Kim S. N., Kim M. R., Sung B. R. S., Kang H. W., Cho M. H., Ryu S. T., 2016, A SUC-Based
Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038mm2, IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, Vol. 24, pp. 794-798
Kim S.N., Kim W., Lee C.K., Ryu S.T., 2012, A 6-bit 3.3GS/s Current-Steering DAC with
Stacked Unit Cell Structure, Journal of Semiconductor Technology and Science, Vol.
12, pp. 270-277
Author
Yi Zhang received the B.S. degree in Microelectronics from Soochow University, Suzhou,
China in 2007.
He received the Ph.D. degree in Circuit and System from RF&OE-ICs, School of Information
Science and Engineering, Southeast University, Nanjing, China, in November 2013.
In the same year, he joined the faculty of the Department of Microelectronics Technology,
Nanjing University of Posts and Telecommunications, Nanjing, China, where he is currently
an assistant professor.
His research interests include analog and mixed signal integrated circuit designs.
Zhonghua Liu received the B.S. degree from Yangzhou University in 1999.
In the same year, he joined Jiangsu Hengxin Technology Co., Ltd., where he is currently
a chief engineer. His Research Orientation is coaxial cables design and improvement.
He won a third prize of Jiangsu Science and Technology Progress Award and two third
prize of Wuxi Science and Technology Progress Award.
Moreover, he has published several papers such as Physical foaming TPX insulated RF
coaxial cable characteristics.
Changchun Zhang received the B.S. and M.S. degrees in communication engineering in
Guilin University of Electronic Technology, Guilin, China, in 2003, and 2006, respectively,
and Ph.D. degree in electrical engineering in Southeast University, Nanjing, China,
in 2010.
Then he worked as a postdoc researcher in Ewha Womans University, Seoul, South Korea.
Since December 2010, he joined Nanjing University of Posts and Telecommunications,
Nanjing, China.
He is a professor in Nanjing University of Posts and Telecommunications, Nanjing,
China. In recent years, he has published more than 50 articles in journals or international
conferences, and held nearly 20 patents for inventions.
His current research interests include IC designs on wireless/wireline transceivers,
and energy harvesters.
Yufeng Guo received the B.S. degree from Sichuan University in 1996.
He received the M.S. degree from the same university in 1999. In June 2005, he received
the Ph.D. degree in Microelectronics from University of Electronic Science and Technology
of China.
He is now a Professor of Nanjing University of Posts and Telecommunications and Dean
of College of Electronic and Optical Engineering & College of Microelectronics.
His research interests include semiconductor power device, micro/nano electronics
devices, RF and power integrated circuits and systems, wireless energy transmission
and ground penetrating radar design.
He owns several awards for teaching and scientific researches and he is the recipient
and co-recipient of the several best paper rewards.
He has published more than 50 papers in his research areas.
Ying Zhang received the B.S. degree in computer application from NUST, China in 2002.
He received the Ph.D. degree in computer application from NUST, China in May 2007.
In 2007, he joined the faculty of College of Electronic and Optical Engineering &
College of Microelectronics at Nanjing University of Posts and Telecommunications,
Nanjing, China, where he is currently a professor.
His research interests include analog/RF integrated circuit designs in CMOS technology
for the applications of body area networks and RF communications.
Xiaopeng Li received the B.S. degree in Communication & Information Engineering and
the M.S. degree in Microelectronics & Solid State Electronics from Southeast University,
Nanjing, China in 2001 and 2006, respectively.
In 2006, he joined the Nanjing Electronic Device Institute, Nanjing, China, where
he is currently a senior engineer.
His research interests include high-speed data converter and ultra-high-speed mixed
signal integrated circuit designs.
Youtao Zhang received the Ph.D. degree in Shanghai Institute of Microsystem and Information
Technology，Chinese Academy of Sciences, in 2005.
Then, he joined the Nanjing Electronic Devices Institute.
His research interests include high-speed analog and mixed signal integrated circuit
designs.
Hao Gao received the B.Eng. degree at the Radio department, School of Information
Science and Engineering, Southeast University, Nanjing, China. In 2008, he received
the M.Sc in electrical engineering from Delft University of Technology, The Netherlands.
In 2015, he received the Ph.D degree in Eindhoven University of Technology.
In 2008, he was a student researcher at Philips Research Headquarter, Eindhoven.
In 2012, he did a European Marie Curie Researcher in Catena Wireless Electronics (Catena
Group, NXP Semiconductor), Stockholm, Sweden.
In 2014, he joined the ELCA-group at Delft University of Technology, The Netherlands,
as a research scientist.
Since 2016 he is an assistant professor at the Technical University of Eindhoven,
The Netherlands.
He was awarded a Philips Semiconductor Scholarship, Delft, 2006.
He was the recipient and co-recipient of the several best paper rewards, including
2011 IEEE MTT-S Radio Wireless Week, 2011 International Conference on Information
and Communications Signal Processing, 2015 ISSCC Distinguished Technical Paper Award,
2018 IEEE MTT-S 2018 International Wireless Symposium.