| Title |
[REGULAR PAPER] A 2 GS/s, 6-bit DAC for UWB Applications In 0.18 ?m CMOS Technology |
| Authors |
Yi Zhang;Zhonghua Liu;Changchun Zhang;Yufeng Guo;Ying Zhang;Xiaopeng Li;Youtao Zhang;Hao Gao |
| DOI |
https://doi.org/10.5573/JSTS.2019.19.6.517 |
| Keywords |
DAC; segmented current steering; UWB; CMOS |
| Abstract |
To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 ?m CMOS technology and the area is 975 μm 775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW. |