Mobile QR Code QR CODE

  1. (Department of Electrical and Computer Engineering, Washington State University, Pullman, WA 99164, USA)
  2. (Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75205, USA)
  3. (Faculty of Engineering, University of Tabuk, Tabuk 71491, Saudi Arabia)
  4. (Department of Information and Communication Engineering, Inha University, Incheon 22212, Korea)

Ionic screening, electrolyte, field-effect transistor, Monte Carlo method, electrical noise


Wireless monitoring (i.e., a biomedical implant) is critical to implement health care systems including non-contact monitoring, bio-signal acquisition, and quick diagnosis. Although these devices have many benefits, there are still plenty of chip design challenges, especially in minimizing the power consumption and silicon area.

Among all the building blocks inside the chips, the PA is one of the most critical blocks since it dissipates large current to achieve higher power amplification. Unlike conventional PAs which operate with large-capacity batteries and mainly focus on linearity enhancement, low power PAs must focus on improving efficiency to prolong battery life.

To improve a PA performance, a current-combing topology [1] was utilized to simplify matching networks and optimize the PA output impedance to the antenna easily. However, high supply voltage and off-chip components degrades the power efficiency and small form-factor. An edge-combining PA [2] was reported to increase power efficiency by using near-threshold supply (i.e., 0.2 V) and a digitally NOR-based phase multiplexer array. However, off-chip bulky components such as capacitors and inductors are still required to maintain the required PA performance.

A class C voltage-shaping PA [3] was reported to achieve high efficiency without harmonic tuning by using a pulse shaping technique. However, different input power make the input capacitance varies among cut-off, subthreshold, and saturation region and thus degrades the power amplifier efficiency.

Fig. 1. Proposed PA with reconfigurable high-gain (HG) and driver-bypass (DB) modes (a) block diagram, (b) schematic.


These PA [1-3] lacks the flexibility of input power tuning range of PA stages. For example, the output power range of a VCO-PA topology and the a VCO, mixer, and PA architecture has huge difference for their input power range, leading to degrade the PA efficiency. To overcome the aforementioned problems, a fully integrated CMOS PA with reconfigurable driving modes is proposed to provide adaptive biasing capabilities for balanced input power range and improve PA efficiency concurrently.

The proposed PA is described in Section II. Section III provides the implementation and the measurement. A conclusion is provided in Section IV.


The schematic of proposed selectable PA using adaptive biasing technique is shown in Fig. 1(a). The circuit is comprised of three building blocks, an adjustable variable amplifier, a low loss 2:1 switch, and an efficient power stage.

For biasing method, the adaptive biasing control technique has been widely used in high output power PA design for linearity and DE enhancement [4-6] as well as temperature compensation [7]. Since the transistors are turning on and off frequently in class C operation, the input capacitance variance leads to the nonlinearity effect (AM-PM distortion) and causes the DE degradation. In the proposed work, the compact adaptive biasing circuit, shown in red in Fig. 1(b), is employed to compensate the input capacitance of M2 and M9. Hence, the DE is increased. Fig. 2 shows the comparison of the proposed PA with conventional resistor biasing and adaptive biasing. The DE increases approximately 7% at the possible operating region, from -6 dBm to -2 dBm. Moreover, the active biasing circuits are formed only with resistors and a transistor. Therefore, little silicon area is needed for employing this technique.

Fig. 2. Simulated DE comparison between fixed and adaptive biasing.


In Fig. 1, M4-M7 form the low loss switching stage. Fig. 3 shows the operating mechanism for a low loss switch that has been proposed in [8]. If the v_control1 is low and v_control2 is high, M4 and M6 turn on and M5 and M7 turn off. The signal (shown in blue) flows through from M6 to C6 and then to the output as shown in Fig. 3(a). On the contrary, the signal (shown in red) flows through from M4 to ground and does not appear at the output end which is shown in Fig. 3(b).

In addition, compared with conventional pass transistor logic (PTL) that only consists of one transistor, the voltage- controlled switch is composed of other two transistors (M4 and M7), which improve the port-to-port (P2P) isolation while maintaining negligible loss. Fig. 4 shows the simulated result of signal loss and P2P isolation of the proposed switch and the PTL. As shown in Fig. 4(a), the loss difference compared with the traditional PTL is only 0.24 dB at 2.4 GHz. Fig. 4(b) shows the simulated result of the P2P isolation. As it can be seen in this figure, the proposed switch improves more than 13 dB isolation ranging from DC to 5 GHz.

Fig. 3. Two modes of control voltage switching mechanism (a) DB mode; V_control1=low, V_control2=high, (b) HG mode; V_control1=high, V_control2=low.


In the proposed deign, the amplifier can operate in two modes depending on the amplitude of the signal from the previous stage. The first mode is DB mode. As shown in Fig. 1(b), if the V_control1 is low and V_control2 is high, the signal passes through C2, M6, and C6 to the power stage. The power stage is designed by using the load pull system to find out the highest DE impedance. After finding the optimum load, L2, L3, C10, C11, and C12 are employed to transform the impedance to the desired matching point. If the signal from previous stages is small, further amplification (HG mode) is required. By changing the gate bias of v_control1 and v_control2, the signal goes through M5 to the power stage. In addition, the current of the driver stage is controlled by the tail current source M1. By tuning the gate bias of M1, the drain-source resistance (Rds) is altered and thus the gain is changed. Moreover, C3 is included to compensate for the loss that caused by the Rds degeneration effect. The proposed driver stage offers a wide power gain from 3 dB to 9.6 dB while adjusting the Vbias from 0.4 V to 0.55 V.

Fig. 4. Simulated results of (a) signal loss, (b) P2P isolation.


The overall efficiency can be obtained as Eq. (1):

\begin{equation*} \mathrm{DE}=\frac{\mathrm{P}_{\mathrm{out}}}{\mathrm{P}_{\mathrm{DC},\,\,\text{driver}\,\,\text{stage}}+\mathrm{P}_{\mathrm{DC},\,\,\text{power}\,\,\text{stage}}} \end{equation*}

where $\mathrm{P}_{\mathrm{out}}$, $\mathrm{P}_{\mathrm{DC},\,\,\text{driver}\,\,\text{stage}}$, and $\mathrm{P}_{\mathrm{DC},\,\,\text{power}\,\,\text{stage}}$ represent the output power, DC power consumption of the driver stage, and DC power consumption of the power stage, respectively. In the DB mode, the $\mathrm{P}_{\mathrm{DC},\,\,\text{driver}\,\,\text{stage}}$ is set to be zero to minimized the overall power consumption to maximize the DE.


The proposed PA was fabricated in a 0.13 ${\mathrm{\mu}}$m CMOS technology. The area of the PA is 1${\times}$0.65 mm$^{2}$ including the measurement pads, as shown in Fig. 5(a). The dc power consumption of the PA is 2.85 mW and 3.86 mW for the DB mode and HG mode, respectively. Fig. 5(b) shows the demonstration setup for the PA measurement. On wafer testing is performed by using Cascode probe station with GSG and PPP probes, Agilent E5071C network analyzer for the continuous wave generation, the Anritsu MA2474D power sensor and Anritsu ML2437A power meter for the PA power measurement.

Table 1. Performance Summary and Comparison













This Work

DB Mode

This Work

HG Mode

Freq (GHz)









$P_{out}$ (dBm)









$P_{dc}$ (mW)









DE (%)


















Process (nm)




















† Only the power amplifier part is taken into account

Fig. 5. (a) Chip micrograph, (b) Measurement setup.


Fig. 6 and 7 shows the result of Pout and DE for the proposed PA. The PA achieves the Pout of 0 dBm with the DE of 35.1% under 0.7 V supply in the DB mode. To provide additional amplification, with varying the vbias, the PA can provide up to 9.6 dB power gain, Pout of 0 dBm while having a DE of 26% under 0.7 V supply, as shown in Fig. 6-8. Noted, the DE is limited by the on-chip passive component with low quality factor, the DE can be improved if the matching network is implement off-chip but with the expense of additional PCB and wire-bonding. In addition, for the $vbias$ is less than 0.4 V, the tail current source goes to the triode region which might induce more nonlinear effect. As the result, the tuning range of $vbias$ lies from 0.4 V to 0.55 V for reliable operation

Fig. 6. Measured output power in DB and HG mode.


Fig. 7. Measured output DE performance in DB and HG mode.


Fig. 8. Measured gain in DB and HG mode.


Table 1 shows a performance comparison with key parameters containing the summary of recent state-of-art works and the proposed PA. Utilizing both adaptive biasing technique and voltage-controlled switch implementation, the proposed design has low power consumption along with tunable high gain and fully integrated passive components compared to the previous state-of-art works that operate in similar frequency band.


A silicon-proved fully integrated tunable PA with adaptive biasing techniques has been successfully implemented. With the adaptive biasing, the DE is improved by 8%. The voltage controlled switch enables dual mode operation to provide either efficient signal transfer or high gain amplification depending on the signal amplitude. The PA has been fabricated in a 130 nm CMOS technology and achieves a DE of 35.1% and 26%, a gain of 1 dB and 9.6 dB under 0 dBm output power for DB mode and HG mode, respectively.


This work was supported by the Inha University Research Grant under Grant INHA-00000.


Kim K., Choi J., Seo M., Nam S., Jun 2014, 500 MHz OOK Transmitter With 22 pj/bit, 38.4% Efficiency Using RF Current Combining, in IEEE Microwave and Wireless Components Letters, Vol. 24, No. 6, pp. 424-426DOI
Tsai Y. L., Lin C. Y., Wang B. C., Lin T. H., May 2016, A 330- µW 400-MHz BPSK Transmitter in 0.18- um CMOS for Biomedical Applications, in IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 5, pp. 448-452DOI
Jeong D., Lee H., Chung T., Lee S., Lee J., Kim B., Aug 2016, Optimized Ultralow-Power Amplifier for OOK Transmitter With Shaped Voltage Drive, in IEEE Transactions on Microwave Theory and Techniques, Vol. 64, No. 8, pp. 2615-2622DOI
Jin S., Park B., Moon K., Kwon M., Kim B., Dec 2013, Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control, in IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 12, pp. 4534-4543DOI
Ryu N., Jang S., Lee K. C., Jeong Y., Jun 2014, CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application, in IEEE Journal of Solid-State Circuits, Vol. 49, No. 6, pp. 1356-1365DOI
Yen Cheng-Chi, Chuang Huey-Ru, Feb 2003, A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer, in IEEE Microwave and Wireless Components Letters, Vol. 13, No. 2, pp. 45-47DOI
Chen S., Yuan J. S., Sept 2011, Adaptive Gate Bias for Power Amplifier Temperature Compensation, in IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 3, pp. 442-449DOI
Lin C. C., Yang J. R., 2014, A 28.5 dBm switched beamforming transmitter for LTE small cell base station application, 2014 International Symposium on Next-Generation Electronics (ISNE), Kwei-ShanDOI
Huang X., Harpe P., Wang X., Dolmans G., de Groot H., 2010, A 0dBm 10Mbps 2.4GHz ultra-low power ASK/OOK transmitter with digital pulse-shaping, 2010 IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA.DOI
Ryu J., Kim M., Lee J., Kim B. S., Lee M. Q., Nam S., 2007A, Low Power OOK Transmitter for Wireless Capsule Endoscope, 2007 IEEE/MTT-S International Microwave Symposium, Honolulu, HIDOI
Liu Y. H., et al. , 2015, 13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802. 15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CADOI


Chung-Ching Lin

Chung-Ching Lin received the B.S. degree in electrical engineering from Tatung University, Taipei, Taiwan in 2012 and M.S. degree in communi-cation engineering from Yun Ze University, Taoyuan, Taiwan, in 2014.

He is currently working toward his Ph.D. degree at Washington State University, Pullman, WA.

His current research includes energy-efficient transmitter and frequency synthesizer design for wireless applications.

Nahid Mirzaie

Nahid Mirzaie received her M.S. degree in Electronics engineering from Iran University of Science and Technology (IUST), Tehran, Iran.

She is currently pursuing her Ph.D. degree in electronics engineering with Southern Methodist University, Dallas, Texas, USA.

Her current research includes yield-aware data converter design and 3D analog/mixed signal circuit design utilizing intelligence algorithms.

Ahmed Alzahmi

Ahmed Alzahmi received the Ph.D. degree in Electrical Engineering from Southern Methodist University, Dallas, TX, USA.

He is currently an Assistant Professor of Electrical Engineering at University of Tabuk, Tabuk, Saudi Arabia.

. His current research interests include the 3-D/2-D memory interface design, RF transceiver design, power delivery network, clock distribution network, and analog/mixed-signal integrated circuit design.

Gyungsu Byun

Gyungsu Byun received the Ph.D. degree in EE from the UCLA, LA. Since 2014.

He is Full Professor and Director of the Mixed-signal Integrated Circuit and System (MICS) Lab with the Dept. of Information and Com- munication of Inha University, Korea.

From 1999 to 2005, he was a Sr. Engineer with Samsung Electronics, where he worked on the design of high speed DRAMs such as DDR2, GDDR3, Rambus and XDR. In 2006, he was a research intern with Intel where he worked on the design of a cache memory and a 3D CMP with RISC core architecture.

From 2007 to 2011, he was a Sr. Engineer with Inphi, where he worked on the design of advanced memory buffer, clocking circuit, and high speed IO circuit design between multi-core CPU and DRAM.

His research area includes analog/mixed-signal IC design for energy-efficient wireless/wireline communication and RF/THz electronics for sensing/imaging and biomedical applications.

He is the author/co-author of over peer-reviewed 61 journal/conference papers and holds 12 US patents in the field of electronic circuits.

Dr. Byun was the recipient of the prestigious NSF CAREER Award (2014), NSF-FRS Award (2013) and the NSF BRIGE Award (2012).