I. INTRODUCTION

In recent years, efficient Watt-level power generation at RadioFrequency (RF) in silicon technologies has become important to support high-speed wireless communications, high-resolution radar, and imaging in military and commercial applications. Lower breakdown voltage of fast transistors limit the output power of single-transistorRF amplifiers to less than 20 dBm. Recent efforts atWatt-level power generation in both silicon CMOS and HBT technologies have relied on large-scale power combining ofsuch <20 dBm amplifier unit cells with <20% peak power-added-efficiency (PAE)^[1-3]. Although advanced CMOS and SiGe technologies provide low-cost, high-yield and high-integration solutions for such systems, the transmit output power is still limited due to the scaling down in transistor sizes and lower breakdown voltages. Therefore, III-V technologies such as GaAs^[4-6], GaN^[7-9] and InP^[10-12] still dominate the power amplifier area at these frequencies despite of their relatively high cost.

Power-combining techniques, such as voltage combining where transformers are used ^[13-15], and current combining where the Wilkinson combiners areused^[16-19], areusually employed to increase the output power of CMOS andSiGe technologies. However, Wilkinson-based and transformer-based power-combining techniques result in relatively high loss when thenumber of combining elements increases, and the free-spacepower-combining technique requires on-chip antennas, which occupy large area on the chip and have a 40%~55% radiationefficiency^[20].

In this paper, in order to obtain high output power, sixteen transistors are paralleled as a super transistor, instead of power-combining techniques. In order to increase the bandwidth of the PA, two L-networks were adopted as the output matching network, and T-type matching network was used as input matching network, in order to reduce the chip area to an extreme.

II. CIRCUIT DESIGN

The proposed PA is designed using 2-µm GaAs HBT process. Adopted transistors in this work all have 5 µm width, 50 µm length and 2 fingers emitter-base junction. The power device combined with 16 unit transistors to obtain high output power. The 2-μm HBT achieves 85-GHz maximum oscillation frequency ($f_{max}$), 40-GHz current-gain cut-off frequency ($f_T$) when biased at $V_{CE}$=4.5 V, and 14-V collector-emitter breakdown voltage. Passive components, including two metal layers, capacitors, resistors, inductances as well as back side via holes are available in the process. Passive and active device models have been implemented and validated by simulation with Agilent Advanced Design System (ADS) software.After frontside wafer fabrication, the 100mm GaAs wafers can be thinned to 100 μm thickness. Compact, high density slot vias together with a metal back-plane are formed to suppress the parallel plate substrate mode.

It is well known that the most practical method for designing a PA is to start with the output stage, and then works backward^[21]. The critical performance specifications and the critical limitations primarily apply to the output stage and its abilities should be the priority. In order to achieve the highest available output power at 6.5~7.5 GHz, the load impedance of main amplifier to the 50Ωload is optimized using load-pull analysis for maximum power transfer at 7 GHz instead of complex-conjugate matching for maximum gain transfer. From the load–pull result, for the optimum fundamental load impedance in terms of maximum output power, is observed to be (6.295+j0.452) Ω with an output power of 31.5dBm, which can be seen in Fig. 1.

The output matching network will present the optimum resistance to the load by transforming the real load impedance of 50 Ω to the optimum resistance. Since the optimum load resistance of the proposed PA is less than 50 Ω, a step down network must be used to transform the PA impedance to the optimum resistance. Fig. 2 illustrates the proposed output matching network to transform the 50Ω load impedance to the desired (6.295-j0.452) Ω, which is the conjugate value of (6.295+j0.452) Ω in order to get the maximum output power. In order to increase the bandwidth of the PA, two L-networks were adopted as the output matching network. The matching network can be divided into the following two sections.

Fig. 1. Simulated power contours for main amplifier.

Fig. 2. output matching network topology.

Fig. 3. Impedance transformation plot.

• Network I is comprised with $L_1$ and $C_1$, where the 50 Ω load is transformed to an intermediate impedance of 26.5 Ω. The impedance transformation plot is shown in Fig. 3.

• Network II consists of $L_2$ and $C_2$, which transform 26.5 Ω to (6.295-j0.452) Ω.

Fig. 4. Schematic of the PA.

Fig. 5. Simulated rollett stability factor.

The schematic of the PA is illustrated in Fig. 4. The PA is composed of an output matching network, a main amplifier, a stability enhancement network, an input matching network and a biased network. The design of T-type or π-type matching networks is usually developed with the intent to achieve wider bandwidth of the networks and hence broadband amplifiers. In the work, T-type matching network is used as input matching network, in order to reduce the chip area to an extreme. In power amplifiers, the bias voltage and current provided to the base of the amplifying transistors determine the class of operation and the linearity of the amplifier response. In order to generate the appropriate bias current and not increase the complexity of circuit design, a simple resister $R_{bias}$ and an inductor $L_{bias}$ were used to generate a steady-state current. The microstrip line $TL$ was used as radio-frequency choke inductor to isolate the influence of radio-frequency signal on the power supply.

The simulated rollett stability factor for the PA is shown in Fig. 5. The rollett stability factor is >1 at DC~10 GHz, which indicates that the PA is unconditionally stable. The PA has a simulated peak small-signal gain of 11.2 dB at 7 GHz with a 3-dB bandwidth of 6.5~7.5 GHz, which can be seen in Fig. 6. The output power ($P_{out}$) versus input power ($P_{in}$) of the PA at 7 GHz is shown in Fig. 7. The power is plotted in dBm, which is the most common unit in which PA power is described. As can be seen, the saturation output power achieves 31 dBm.

Fig. 6. Simulated gain versus frequency.

Fig. 7. Simulated output power versus input power.

III. MEASURED RESULT

In this design, the eventual sizes of capacitors, resistors, inductor and transmissions lines are determined by simulations and optimizations in ADS software. Furthermore modifies has been carried out for all transmission lines based on the electromagnetic simulations. The chip photo of proposed GaAs HBT PA is shown in Fig. 8 with a size of 1.8×0.7 $mm^2$. In order to maximize the gain, the back-via holes at emitter of main transistor are paralleled for reducing parasitic inductance effects.

Fig. 8. The chip photo of the designed PA.

Fig. 9. Measured S-parameters versus frequency.

The proposed PA is measured via on-wafer with 150 µm spacing GSG RF probing arms. The supply voltage $V_{DD}$ of 5 V and the biased voltage $V_{bias}$ of 3 V are provided by Agilent E3633A power supply and Agilent 66319D DC source, respectively. The quiescent current of the PA is 557 mA. S-parameters performance are measured using Agilent N5224A microwave network analyzer. Large signal characterization has been carried out with continuous-wave (CW) signal using Agilent N5183A microwave Analog signal generator, E4417A power meter and N9030A signal analyzer.

The measured small signal S-parameters of this watt-level broadband PA are shown in Fig. 9. The PA has a maximum small signal gain ($S_{21}$) better than 12 dB, and a 1.1 GHz 3-dB bandwidth from 6.0 to 7.1 GHz due to the bandwidth enhance technology of PA circuit with broadband matching network. The center frequency is slightly shifted up from the designed 7 GHz to 6.55 GHz due to process variations. The input and output reflection coefficients are less than -6 dB and -8 dB over the range of 6.0~7.1 GHz, respectively. Measurements agree with simulations versus frequency, which shows the accuracy of the ADS software and the electromagnetic models.

Fig. 10. Measured power gain and PAE at 6.6 GHz.

Fig. 11. Measured peak PAE and saturation output power verse frequency.

The measured power gain and PAE are plotted in Fig. 10. Fig. 10 shows the measured large-signal performance of the prototype with 41 % peak PAE at 6.6 GHz with 12.1±0.2 dB of large-signal power gain. For broadband performance, PAE and saturation output power ($P_{sat}$) have been measured in the frequency from 6.0 to 7.1 GHz, which is given in Fig. 11. The output power is higher than 29.5 dBm from 6.0 to 7.1 GHz , and PAEs are all better than 28% over the range of 6.0~7.1 GHz. At 6.6 GHz, the peak PAE and $P_{sat}$ are 41% and 31.4 dBm, respectively.

Measured results are compared to recent literatures in Table 1^[22-24], the proposed PA exhibits the widest bandwidth and smallest die area, while showing the maximum saturation output power.

IV. CONCLUSION

In this paper, the design and the performance of a Watt-level wideband PA have been presented. In order to obtain high output power, sixteen transistors are paralleled as a super transistor, instead of power-combining techniques.PA design is to start with the output stage, and then works backward. The PA has a maximum small signal gain better than 12 dB, and a 1.1 GHz 3-dB bandwidth from 6.0 to 7.1 GHz. At the center frequency of 6.6 GHz, the PAE and $P_{sat}$achieve 41% and 31.4 dBm, respectively. The designed circuit can satisfyhigh-efficiency and high-output-power requirements for 6.0~7.1 GHz applications.