InoueToshiyuki
NomuraKohei
NoguchiRyosuke
KodaNatsuyuki
TsuchiyaAkira
KishineKeiji
-
(Department of Electronic Systems Engineering, The University of Shiga Prefecture,
Hikone, Shiga 522-8533, Japan)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Optical fiber communication, transceiver circuit, PLL, FPGA, labeling
I. INTRODUCTION
The amount of data traffic has been increasing due to rapid diffusion of smartphones
and tablet PCs (1). Therefore, increasing channel capacity is required in optical fiber communication
systems. Since modulation speed reaches the upper limit of 25 Gb/s and further improvement
is quite difficult in non-return-to-zero systems, a wavelength-division multiplexing
technique has been adopted for 40 GbE and 100 GbE to increase the transmission capacity
(2,3). In addition, multi-level modulation techniques, such as pulse amplitude modulation
(PAM) and quadrature amplitude modulation (QAM), have been developed and studied (4-6). For example, PAM4 will be adopted for 400 GbE according to the IEEE standardization
activity (7,8).
In optical fiber networks, additional data called “labels” or “headers” are attached
to continuous bit streams (payloads) for switching channels and monitoring networks
(9-11). If additional data can be multiplexed to frame signals arbitrarily in current systems,
the capacity and improving quality of data transmission will increase. However, data
communication is usually based on specific standards such as synchronous optical network/
synchronous digital hierarchy (SONET/SDH) (2, 10-13) and Ethernet (14,15), and the configurations of data frames are defined in these standards. In the case
of using a larger frame and embedding additional data, it is necessary to read and
store the original frames by using a processor, and then the frames should be rewritten
with the additional data. Therefore, the load of the processor is increased, and the
transmission delay occurs. In addition, replacing current systems with modified systems
and changing the standards are required, which will lead to increased costs for designing
and introducing such systems. In the case of using additional packets for labeling,
the effective bit rate of payloads is decreased because the additional packets are
inserted between frames.
We previously proposed the labeling signal transmission system shown in Fig. 1 (16-19). In this system, the frame signal with a label for routing is transmitted, and the
original frame signal is routed to the specific path in accordance with the added
label. As shown in Fig. 1, labels (A), (B), (C) are related to the amount of frequency shift, ${\Delta}$$_f{\mathrm{A}}$,
${\Delta}$$_f{\mathrm{B}}$, ${\Delta}$$_f{\mathrm{C}}$ in frequency modulation. In
a transmitter, the original frame signal is frequency modulated by a modulator (MOD)
in accordance with the label. In a receiver, the original frame signal and labeling
data are extracted using a clock and data recovery circuit (CDR) (20-25) and a demodulator (DEMOD) consisting of a delay detection circuit (16-18). The extracted frame signal is routed to the path with the same label as the extracted
label with a selector (SEL). This system enables us to transmit additional information
without changing the configuration of the frame signal. We demonstrated the frequency-modulation/demodulation
circuits for these systems with 10-Gb/s frame signals on 65-nm CMOS chips and discrete
devices (16-19). However, this conventional system is not suitable for additional data transfer and
its application is limited to routing since label information cannot be changed rapidly.
Also, the number of labels is limited by the variable range of the frequency shift
and resolution of a DEMOD, so it is difficult to prepare many labels.
Fig. 1. Our conventional labeling signal transmission system. CDR, MOD, DEMOD and
SEL stand for clock and data recovery circuit, modulator, demodulator, and selector,
respectively.
We then proposed a new binary labeling signal transmission system shown in Fig. 2 (26). In this system, an additional frame signal (binary data) can be transmitted with
the original frame signal. The state of “0” or “1” of the additional frame signal
is related to the modulation or non-modulation of the original frame signal, and the
original frame signal is modulated in accordance with the additional data in a transmitter.
In a receiver, the additional data are demodulated by detecting whether the original
frame signal is modulated. In this system, the frame configuration is not changed
since the frame signals are only modulated and demodulated. Consequently, the additional
data can be transmitted without decreasing the effective bit rate of payloads, and
the proposed system can coexist with the current systems.
Fig. 2. Newly developed binary labeling signal transmission system.
In the previous research (26), we introduced a concept of a stabilization technique called “digital smoothing”
so that a phase-looked loop (PLL) circuit (27-31) could maintain a synchronous state because the implemented system had suffered from
bit error of the frame signals arising from an asynchronous operation of the PLL.
However, the validity of the smoothing has not been verified yet.
In this study, we implemented and evaluated the improved binary labeling signal transmission
system with the digital smoothing. First, we discuss our designed modulation-system
protocol for our system. Next, we explain the operating principles of a transmitter
and receiver. After that, we analysis the effect of the digital smoothing theoretically.
Then, we present an implementation of the improved system by combining field-programmable
gate arrays (FPGAs) and discrete devices of a delay flip-flop (D-FF), voltage-controlled
oscillator (VCO), and a low-pass filter (LPF) from the viewpoint of design flexibility.
Finally, we show the experimental results from evaluating the implemented system and
verify the effectiveness of the digital smoothing.
II. CONFIGURATION OF LABELING SIGNAL TRANSMISSION SYSTEM AND MODULATION-SYSTEM PROTOCOL
The configuration of our newly developed binary labeling signal transmission system
is shown in Fig. 2. This transmission system is composed of a transmitter for adding information to
frame signals and a receiver for extracting original frame signals and the added information.
In this system, two states of frame signals, i.e., non-modulated and modulated, are
used. The non-modulated and modulated states correspond to the low level (“0”) and
high level (“1”) of the labeling signals, respectively.
Fig. 3 shows the frame configuration for our newly developed binary labeling signal transmission.
The labeling signal is composed of two sections. The first 1-bit is a synchronous
signal to detect the starting point of the labeling signal, and the frame signal is
frequency modulated in this section. The following bits are payload with a data width
of x-bits. When the labeling signal is “1”, the frame signal is frequency modulated.
On the other hand, the frame signal is not modulated when the labeling signal is “0”.
Therefore, binary data are multiplexed to the original frame signal by using the modulated
and non-modulated states.
Fig. 3. Frame configuration of binary labeling signals.
III. DESIGN OF TRANSMITTER CIRCUIT
1. Configuration of Transmitter Circuit
Fig. 4 shows a block diagram of a transmitter. The transmitter is composed of a D-FF that
generates a modulated frame signal and PLL circuit that generates a frequency-modulated
clock signal for the D-FF. Frame signals are input to the D-FF using frequency-modulated
signals as the clock signals, and a modulated frame signal is generated. By modulating
the frame signals in accordance with the labeling signals, the labeling-signal information
is multiplexed.
Fig. 4. Block diagram of transmitter.
2. Operation Principle of Modulating Frame Signal
Fig. 5 shows the timing charts of the D-FF outputs. When the clock signal is not frequency
modulated, non-modulated frame signals are output, as shown in Fig. 5(a). As shown in Fig. 5(b), however, when the frequency-modulated signal is used as the clock signal, modulated
frame signals are output.
Fig. 5. Timing charts of D-FF outputs when (a) using non-modulated, (b) modulated
clock signals.
Next, the effect of the phase difference of the clock signal on the D-FF is considered.
The timing chart of the D-FF using the modulated clock signal is shown in Fig. 6. When the phase difference from the ideal position of the falling edge (the center
of the bit) ${\Delta}$${\phi}$ is $π$ (equivalent to the half of 1-bit width) or less,
the frame signal is modulated and the bit rate is changed, but the binary information
of the D-FF output is the same as that of the D-FF input (original frame signal),
as shown in Fig. 6(a). When the phase difference is larger than $π$, the clock signal detects the previous
or next bit information of the frame signal. As a result, bit error occurs and the
output data frame remain changed, as shown in Fig. 6(b). Therefore, it is necessary to set the frequency-shift amount for frequency modulation
so that the phase difference will not exceed $π$.
Fig. 6. Comparison between timing charts when (a) ${\Delta}$${\phi}$ ${\leq}$ $π$,
(b) ${\Delta}$${\phi}$ > $π$.
3. PLL Circuit with Variable Divider
To generate frequency-modulated clock signals, a PLL circuit with a variable divider
is used as a synthesizer. Fig.~7 shows the configuration of the PLL circuit. The frequency
of the VCO output, $_f{\mathrm{VCO}}$, can be written as
where $_f{\mathrm{r}}$ is the frequency of the reference signal input to an EXOR,
${N}$ is the center division ratio, and ${a}$ is the variation in the division ratio,
respectively. When the ratio of the variable divider is changed, i.e., ${N}$ ${\rightarrow}$
(${N}$ + ${a}$) ${\rightarrow}$ ${N}$ ${\rightarrow}$ (${N}$ ${-}$ ${a}$) ${\rightarrow}$
${N}$ ${\rightarrow}$ (${N}$ + ${a}$) ${\rightarrow}$${\dots}$, the frequency of the
VCO output is also changed. In other words, we can modulate the clock signal by changing
the division ratio.
Fig. 7. Configuration of PLL synthesizer with variable divider.
4. Modulation-control Circuit for Multiplexing Labeling Signal
The configuration of our designed modulation-control circuit is shown in Fig. 8. We designed a PLL circuit with two feedback paths. One path has a divider with a
fixed ${N}$, and the other has a variable divider with ${N}$ ${\pm}$ ${a}$. Modulation
or non-modulation can be selected by switching the feedback path in accordance with
the labeling signal. The operation of the PLL circuit is shown below.
Fig. 8. Selecting (a) non-modulation, (b) modulation by switching feedback path.
(1) For labeling signal “0”, the feedback path with a fixed divider is selected using
a SEL, and the PLL circuit oscillates at a center frequency, $_f{\mathrm{c}}$ = ${N}$
${\times}$ $_f{\mathrm{r}}$, as shown in Fig. 8(a). Since the clock signal for the D-FF is not modulated, the D-FF outputs non-modulated
frame signals.
(2) For labeling signal “1”, the feedback path with the variable divider is selected,
and the PLL circuit oscillates at $_f{\mathrm{VCO}}$ = (${N}$ ${\pm}$ ${a}$) ${\times}$
$_f{\mathrm{r}}$, as shown in Fig. 8(b). Since the clock signal is modulated by changing the division ratio of the variable
divider, the D-FF outputs frequency-modulated frame signals.
5. Importance of Digital Smoothing Technique
The timing chart of the PLL circuit with two feedback paths is shown in Fig. 9. When the feedback path is switched from the fixed divider path to the variable divider
path, the ratio of the variable divider may be changed to (${N}$ ${\pm}$ ${a}$) in
the middle of the cycle of outputting $_f{\mathrm{r}}$ from the ${1/N}$ divider, as
shown in Fig. 9. In this case, the duty ratio of the EXOR output changes irregularly. Since the LPF
output also change irregularly, the PLL circuit enters an asynchronous state. Consequently,
the phase difference of the clock signal (VCO output) for the D-FF exceeds the phase
margin, and the bit error in the output frame signal occurs. To remove this defect,
the feedback path should be changed when the ratio of the variable divider is ${N}$,
as indicated by the yellow regions (acceptable regions) in Fig.~10. As a result, the
SEL output is switched seamlessly, and the PLL circuit can remain in the synchronous
state. Therefore, it is necessary to shift the rising edge of the labeling signal
to an acceptable region.
Fig. 9. Timing chart in PLL circuit with two feedback paths.
Fig. 10. Solution to prevent PLL circuit from entering asynchronous state.
We then developed a switching timing adjustment technique called “digital smoothing”
for shifting the edge timing of labeling signal to the appropriate timing. The configuration
of the PLL circuit with the digital smoothing technique is shown in Fig. 11. We use another D-FF for the timing adjustment and a synchronous clock having a period
of $T_{\mathrm{cycle}}$. Here, $T_{\mathrm{cycle}}$ is set to
As shown in Eq. (2), the time of one cycle (${N}$ ${\rightarrow}$ (${N}$ + ${a}$) ${\rightarrow}$ ${N}$
${\rightarrow}$ (${N}$ ${-}$ ${a}$)) in the variable divider is equal to the total
time of four cycles in the fixed divider. Therefore, the phase of the variable divider
output corresponds to that of the fixed divider output in the region with the division
ratio of ${N}$. The timing chart of the digital smoothing technique is shown in Fig. 12. When the falling edge of the synchronous clock is adjusted to the region where the
ratio of the variable divider is ${N}$, the rising edge of the labeling signal can
be shifted to an acceptable region by using the D-FF and clock. Since the SEL output
is switched seamlessly, the PLL circuit can remain in the synchronous state. Consequently,
the digital smoothing technique can prevent bit errors in the frame signal from occurring.
Fig. 11. Configuration of PLL circuit with digital smoothing technique.
Fig. 12. Timing chart of PLL circuit with digital smoothing technique.
IV. DESIGN OF RECEIVER CIRCUIT
Fig. 13 shows a block diagram of a receiver circuit. The original frame signal is extracted
from the modulated frame signal by using a CDR. The additional binary data are also
extracted using a demodulation circuit. This demodulation circuit has the three functions
of modulation detection, synchronization, and demodulation. The timing chart of the
demodulation circuit is shown in Fig. 14. The modulation-detecting circuit outputs detecting signals by checking whether the
received frame signal is modulated. By detecting a synchronous signal, the starting
point of the labeling signal is recognized. Then, the payload information is read
out and the labeling signals are demodulated.
Fig. 13. Block diagram of receiver.
Fig. 14. Timing chart showing demodulation flow.
1. Frequency-modulation Detection
The timing chart of the modulation-detecting circuit is shown in Fig. 15. This circuit measures the high-level duration of the received frame signal. The
minimum duration of the non-modulated frame signal with the bit rate $_f{\mathrm{r}}$
is ${\tau}$$_{\mathrm{r}}$ =$1/_f{\mathrm{r}}$. As the frequency of the frame signal
becomes higher, the high-level duration becomes shorter. The detecting signal is set
to “1” if the duration is less than $1/_f{\mathrm{r}}$; otherwise, it is set to “0”.
Therefore, frequency modulation can be detected.
Fig. 15. Operation of modulation-detecting circuit.
2. Synchronization and Demodulation of Labeling Signal
The operation of the labeling-signal demodulator is shown in Fig. 16. If the detecting signal becomes high-level multiple times, the frame signal is recognized
as being modulated and the demodulator output is set to “1”. If not, the frame signal
is recognized as being non-modulated and the output is set to “0”. Because our designed
modulation-system protocol consists of a 1-bit synchronous signal and x-bits payload.
The circuit first detects the synchronous signal. Then, reading out information of
the payload starts after waiting the time of 1-bit width. In other words, the demodulator
does not output “1” when the synchronization signal is detected. Thus, the received
modulated frame signal can be synchronized, and the labeling information can be demodulated
bit by bit.
Fig. 16. Operation of labeling-signal demodulator.
V. EXPERIMENTAL RESULTS
We implemented the transceiver circuit described in the previous sections. The implemented
transceiver circuit is shown in Fig. 17. The transceiver consists of a transmitter (frequency-modulation circuit) using an
FPGA, discrete devices (VCO, EXOR, and LPF), and a receiver (frequency-demodulation
circuit) using an FPGA. The output signals were measured using an oscilloscope.
Fig. 17. Experimental setup for evaluating our newly developed labeling signal transmission
system.
1. Transmitter
We first examined the operation of the frequency modulation for frame signals. Square
waves with 250 kHz (500 kb/s) were used as the frame signals. The $_f{\mathrm{r}}$,
${N}$, and ${a}$ were set to 50 kHz, 10, and 1, respectively. The measurement results
of the transmitter circuit are shown in Fig. 18. When the labeling signal was “0”, the waveform of the D-FF output was almost the
same as that of the input signal, as shown in Fig. 18(a). The position of the rising/falling edges of the D-FF output did not change. Conversely,
when the labeling signal was “1”, the position of the edges changed in comparison
with (a), as shown in Fig. 18. These results indicate that the frame signal was modulated.
Fig. 18. Waveforms of D-FF outputs (a) without modulation, (b) with modulation.
Next, we evaluated the validity of the proposed digital smoothing technique. The LPF
outputs (VCO inputs) were measured when the labeling signal was shifted from “0” to
“1”. The measurement results are shown in Fig. 19. When the digital smoothing technique was not used, the LPF output was not periodic,
as indicated with a white circle in Fig. 19(a). This causes asynchronization of the PLL circuit since the frequency of the VCO changes
irregularly. When using the smoothing technique, however, the LPF output became periodic,
as indicated with a red circle in Fig. 19(b). This means that the PLL circuit can remain in a synchronous state and the output
frequency changes regularly.
Fig. 19. Waveforms of PLL circuit (a) without, (b) with digital smoothing technique.
Fig. 20 shows the waveforms of the modulated frame signal. Although the square wave with
duty ratio of 1:1 was input to the D-FF, the modulated frame signal without the smoothing
technique was not the same as the input signal, and bit error occurred, as indicated
in Fig. 20(a). By using the digital smoothing technique, bit error was prevented, as shown in Fig. 20(b). We verified that a frame signal can be modulated without changing the information
of that signal by using the designed transmitter circuit.
Fig. 20. Waveforms of D-FF outputs (modulated frame signals) (a) without, (b) with
digital smoothing technique.
2. Receiver
We extracted the labeling signal added to a frame signal by using the implemented
receiver. The bit rate of the labeling signal and length of the payload were set to
3 kb/s and 10 bits, respectively. We first examined frequency-modulation detection
in the received frame data. The measurement results are shown in Fig. 21. The detecting signal became high level when the labeling signal was “1”, and frequency
modulation was accurately detected. We then examined the demodulated labeling signal.
Fig. 22 shows the measured demodulator output. The 10-bit payload of the labeling signal
(“0101010101”) multiplexed on the frame signal was demodulated without bit error.
From this result, labeling signal transmission was achieved by using the implemented
transceiver based on the designed modulation-system protocol.
Fig. 21. Waveforms of modulation-detecting circuit.
Fig. 22. Waveforms of binary data DEMOD.
VI. DISCUSSION
In this section, we consider the theoretical limitation of the maximum bit rate of
labeling signal transmission. As mentioned in Sect. 3.5, the time of one cycle in
the variable divider, $T_{\mathrm{cycle}}$, can be expressed with Eq. (2). Therefore, the minimum width of a 1-bit labeling signal is $T_{\mathrm{cycle}}$,
and the maximum bit rate, $R_{\mathrm{max}}$, is given by
Since an EXOR can compare the phase difference of $π$ or less, ${a}$ should satisfy
where ${N}$ should be as large as 4. Using the center frequency of the PLL circuit,
$_f{\mathrm{c}}$ = ${N}$ ${\times}$ $_f{\mathrm{r}}$, we can obtain
Hence, using Eqs. (3, 5), the maximum bit rate can be calculated as
Assuming that $_f{\mathrm{c}}$ = 10 GHz, $_f{\mathrm{r}}$ should be less than 2.5
GHz, and the maximum additional bit rate of 625 Mb/s can be obtained in our newly
developed labeling signal transmission system.
The performance of our system is summarized and compared with that of the related
technique using optical labeling (11) in Table 1. Our proposed system was demonstrated by using low bit rates (500 kb/s for frame
signals and 3 kb/s for additional signals) due to limitation of operating frequency
of discrete devices (D-FF and VCO) and an internal clock in FPGA boards we used. In
CMOS ICs for optical communication systems, D-FFs and VCOs operate at 25 GHz or higher
frequency (32). Furthermore, FPGA boards operating in several dozens of Gb/s are commercially available
(33). Therefore, the proposed system can be applied to 10 Gb/s or faster.
Table 1. Performance summary and comparison
|
Technique
|
Domain
|
Bit rate
|
|
Payload
|
Labeling
|
|
Binary labeling
(This work)
|
Electrical
|
500 kb/s
|
3 kb/s
|
|
10 Gb/s
|
< 625 Mb/s*
|
|
Optical labeling [11]
|
Optical
|
2.5 Gb/s
|
155 Mb/s
|
VII. CONCLUSIONS
We implemented and evaluated our newly developed binary labeling signal transmission
system. We designed a modulation-system protocol and proposed a digital smoothing
technique for stabilizing PLL operation. We confirmed that the bit error of modulated
frame signals could be prevented by using our proposed digital smoothing technique
in the transmitter. The labeling signal multiplexed to a frame signal was demodulated
without bit error. It was theoretically confirmed that transmitting additional information
with hundreds of Mb/s is possible with our system.
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Author
Toshiyuki Inoue received the B.S., M.S. and Ph.D. degrees in Electrical Electronic
and Information Engi-neering from Osaka University, Osaka, Japan in 2010, 2012 and
2015, respectively. He joined the Depart-ment of Electronic Systems Engi-neering,
The University of Shiga Prefecture, in 2017, and has been an Assistant Professor since
2017. His research interests include RF circuits for wireless communication, wireless
sensor networks, radio-over-fiber technique and optoelectronics. Dr. Inoue is a member
of the Institute of Electronics, Information and Communication Engineers (IEICE) of
Japan and the Japan Society of Applied Physics (JSAP). He received the Paper Award
in 2013 from IEICE.
Kohei Nomura received the B.S. degree of electronic systems engi-neering from The
University of Shiga Prefecture in 2016. Since the same year, he has enrolled a master's
course Graduate School of Engi-neering in the University of Shiga Prefecture. His
research interest includes an FPGA based circuits and systems.
Ryosuke Noguchi received the B.S. degree of electronic systems engi-neering from the
University of Shiga Prefecture in 2017. Since the same year, he has enrolled a master's
course Graduate school of Engi-neering in the University of Shiga Prefecture. His
research interest includes ultra-high-speed CMOS circuits for optical fiber communications.
Natsuyuki Koda received the B.S. degree in electronic systems engi-neering from the
University of Shiga Prefecture in 2016. The same year, he enrolled in a master’s course
at the Graduate School of Engineering in the University of Shiga Prefecture. His research
interest includes high-performance RF communications systems.
Akira Tsuchiya received the B.E., M.E. and Ph.D. degrees in Commu-nications and Computer
Engineering from Kyoto University, Kyoto, Japan, in 2001, 2003, and 2005, respectively.
Since 2005, he has been an Assistant Professor in the Department of Communications
and Computer Engineering, Graduate School of Informatics, Kyoto University. Since
2017, he has been an Associate Professor in the Department of Electronic Systems Engineering,
the University of Shiga Prefecture, Shiga, Japan. His research interest includes modeling
and design of on-chip passive components of high-frequency CMOS, and high-speed analog
circuit design. He is a member of the IEEE, IEICE and IPSJ.
Kishine Keiji received the B.S., and M.S. degrees in engineering science from Kyoto
University, Kyoto, Japan, and Ph.D. degree in informatics from Kyoto University, Kyoto,
Japan, in 1990, 1992, and 2006, respectively. In 1992, he joined the Electrical Communication
Laboratories, Nippon Telegraph and Telephone Corporation (NTT), Tokyo, Japan. He has
been engaged in research and design of high-speed, low-power circuits for Gb/s LSIs
using Si-bipolar transistors, with application to optical communication systems in
NTT System Electronics Laboratories, Kanagawa, Japan. From 1997, he has been worked
on research and development of over Gb/s Clock and Data Recovery IC at Network Service
Innovation Laboratory in NTT Network Innovation Laboratories, Kanagawa, Japan. He
worked at Ubiquitous Interface Laboratory in NTT Microsystems Integration Laboratories,
Kanagawa, Japan. Since 2008, he had been an Associate Professor, and now he is a Professor
with the school of engineering, the University of Shiga prefecture, Shiga, Japan.
Dr. Kishine is a member of the IEEE Solid-State Circuits Society (SSCS) and Circuits
and Systems (CAS), the Institute of Electronics, Information and Communication Engineers
(IEICE) of Japan, the Institute of Electrical Engineers of Japan (IEEJ).