I. INTRODUCTION

The continual growth in processing power of GPU for machine learning server and the increasing demand for Giga Ethernet services makes a need for higher bandwidth data transmission. In order to satisfy with the need, industrial standards are being developed in terms of the channel characteristics and interface electrical specifications of short channel (on-board) and long channel (inter-card) for serial transmitter at data rates of 10-Gb/s or above, which results in developing package techniques on board for reducing channel loss. However, power efficiency transmitters have to be needed because of the limitation of material for PCB. For high-speed data transmission, as shown in Fig. 1, there are typically two drivers such as current mode logic (CML) and Source-series-terminated (SST) output driver.

Fig. 1. Schematic of (a) current-mode logic (CML), (b) sourceseries terminated (SST) output driver.

A type of CML output driver is frequently employed because they support high data rates and have an inherently low susceptibility to power supply noise ^(1-3). However, these advantages come along with some drawbacks such as the static power consumption and the inability to support different dc termination. Moreover, the more CML output driver compensates for channel loss, the more the static power consumption increase and the amplitude of output swing decrease. In order to reduce the static power consumption, SST driver that is one of voltage-mode drivers comes up in high-speed interface area, which leads to supporting many different termination voltages combined with a higher signal swing without the static power consumption ^(4,5). As a result, the SST driver is able to reduce power consumption up to 4 times. However, as shown in Fig. 2, the voltage-mode drivers for low power consumption generally have degraded transmit equalization and overheads associated with maintaining proper source termination and power supply noise, which results in increasing the dynamic power consumption and deteriorating noise immunity because of the increase in complexity of pre-driver and digital logic ⁽⁶⁾. For these reasons, communication systems that need high susceptibility in terms of power supply noise prefer current-mode drivers to voltage-mode drivers. Therefore, in this paper, the current-mode output driver having reconfigurable capacitive peaking is proposed for low power consumption and low susceptibility about power supply noise.

Fig. 2. Schematic of conventional SST pre-emphasis driver.

Section II describes the conventional CML pre-emphasis driver. Section III presents the proposed CML pre-emphasis driver using reconfigurable capacitive peaking method. Section IV and V show the post-simulation results and conclusion.

II. Conventional CML Pre-emphasis Driver

Fig. 3 shows the implementation of conventional half-rate two-tap pre-emphasis and de-emphasis method for CML driver ⁽⁴⁾. It is easy to modify the amplitude of output swing into current-mode adder including controllable gain. If D0 that is current data is equal to D1 that is 1-Unit Interval (UI) delayed data, the amplitude of output swing is VDD-($I_{1}$ X R) and VDD-($I_{0}$ X R) at the OUTP and OUTN, which is called for de-emphasis to reduce low-frequency components. If D0 is not equal to D1, the amplitude of output swing is VDD and VDD-(I0+I1) X R at the OUTP and OUTN, which is called for pre-emphasis to enhance high-frequency components. Basically, there is a basic rule for deciding the equalization gain, if the power of interested signal is reduced up to -6 dB, the eye of the signal is able to be closed. For example, there is a differential signal having the amplitude about 1V. The signal pass through the channel that has the loss below -6 dB at the interested frequency, which results that the amplitude is reduced up to 500 mV. Because of this reason, the eye of the signal is closed. Therefore, so as to sufficiently open the eye of the signal, the sum of the equalization gain of pre-emphasis driver and the channel loss including the loss of SMA and transmission line has to be larger than -6 dB. Consequently, the more the channel loss increases, the more the equalization gain of the driver is required, which results in increasing power consumption for CML. Additionally, increasing current for taps causes power consumption of other circuits. In the case of the CML type driver, in order to increase the equalization gain of the driver, the current for main cursor or the current for post cursor should be increased. Increasing the current of each cursor causes the drain voltage of the current source to be reduced, which results that the input transistor of driver is not able to be totally turned off. Because of this reason, the width of the input transistor has also to be increased and the parasitic capacitance of input transistor is also increased, which causes the power consumption of the pre driver to be increased in order to drive the input transistor of the driver. Therefore, there is a trade-off relationship between overall power consumption and the ability to compensate for channel loss.

Fig. 3. Block diagram of implemented half-rate conventional CML driver.

III. Proposed CML Pre-emphasis Driver using Reconfigurable Capacitive Peaking Method

The proposed output driver is shown in Fig. 4. As the implemented conventional two-tap CML output driver, the proposed also employs half-rate two-tap pre-emphasis and de-emphasis structure with the same of current. It is just changed in terms of output driver. Capacitor bank that consists of eight capacitors is just added at the node of CML driver output in order to increase the ability to compensate for the channel loss. Unlike that the equalization gain of the conventional one can be changed by increasing or decreasing the amount of current for main and post cursor, the equalization gain of the proposed pre-emphasis can be varied from 4 dB to 15.2 dB without increasing the amount of current source for main and post cursor because the proposed uses the energy from the capacitor bank. Based on conservation law, the variation of voltage at the bottom plate capacitor has an effect to the top plate of capacitor, which results in increasing the equalization gain of pre-emphasis. Thus, the method for increasing the equalization gain of pre-emphasis can be called capacitive peaking ^(7-9). In order to implement this method, the high threshold voltage MOSFET is used. Because the level of swing for CML driver is typically from VDD to the VDD-I X R, it is for MOS switches not to be able to turn on and off. Due to this reason, the switches for capacitive peaking in the proposed pre-emphasis CML driver are realized with high threshold voltage MOSFET. And the pre driver for the switched for capacitive peaking consumes more 1.5 times in order to increase the amplitude of swing. Even if the conventional one dissipates the current and the amplitude of swing in order to increase the ability of equalization gain, the proposed one just adds the pre driver having more power consumption to the output node, which results in reducing the overall power consumption. As shown in Fig. 4, through the pre- driver, the data without 1-UI delay is just connected with the gate of MOS switches. The data in phase is connected with the gate of MOS switches at the OUTN and the data out of phase is connected with that of MOS switches at the OUTP, which causes to charge and discharge at the bottom plate of the capacitor. The operation of the proposed is shown in Fig. 5. When the data in phase is low, the bottom plate of capacitor is charged to VDD. And when the data in phase is high, the bottom plate of capacitor is discharged to GND. This variation at the bottom plate of capacitor increases the gain of pre-emphasis at the OUTN when the output signal is changed from VDD to GND. At the OUTP, the method to increase the gain of pre-emphasis is same. Even if the capacitor bank improves the overall gain of CML driver, the impedance matching may have the problem. In this driver, there is a cap bank that includes that the number of capacitors is eight. The unit capacitance is 50 fF. In the worst case that the eight capacitances are connected with VDD, the value of effective termination resistance is about 41 ohm. However, because the pseudo random binary sequence (PRBS) includes frequency components from low frequency to high frequency domain. The average value of effective termination resistance is almost 50 ohm. Therefore, the total capacitance can be negligible in terms of impedance matching.

Fig. 4. Block diagram of half-rate proposed CML driver.

Fig. 5. Operation of proposed CML driver.

IV. RESULTS

The proposed driver is implemented in 55 nm CMOS process. The area of proposed driver, as shown in Fig. 6, is 320 ${\mu}$m ⅹ163 ${\mu}$m. The data rate of the proposed is 10-Gb/s with the supply voltage of 1.2 V. A channel with insertion loss of -12.3 dB at 5 GHz is employed to test the driver and a $2^{31}$-1 PRBS is applied to the input of driver. As shown in Fig. 7, the change of equalization gain for pre-emphasis driver is from 4 dB to 15.2 dB by just changing the number of capacitors. Additionally, according to the change of post cursor current source, the ability to compensate for the channel loss is able to be improved. The conventional one is set with the amount of main and post current source for being able to compensate -10 dB channel loss. The proposed one is set with the amount of current source for compensating -4~dB channel loss. And, in order to improve the ability to compensate for the channel loss, the five capacitors are connected with at the output node. As a result, the eye height and width of the proposed driver is clearly improved than the conventional one as shown in Fig. 8. An eye height of 160 mV and an eye width of 0.92UI are achieved. The width of eye diagram for the proposed is improved about 28.2% compared with the conventional. As shown in Table 1, compared with the conventional one, the power consumption of the proposed can be reduced by 56.32 %. Thus, these results show that the proposed output driver is able to reduce the overall power consumption and increase the ability to compensate the channel loss by using reconfigurable capacitive peaking.

Fig. 6. Layout of the proposed driver.

Fig. 7. Variation of equalization gain of pre-emphasis driver according to the number of capacitors.

Fig. 8. (a) Eye diagram of the conventional one, (b) of the proposed one.

V. CONCLUSION

A 10-Gb/s two-tap current mode logic driver using reconfigurable capacitive peaking is proposed for -12.3~dB insertion loss. The equalization gain of pre-emphasis for CML driver is controlled by the number of capacitor without additional current source. Additionally, because the control of gain is decided by the number of capacitor, the realization and expandability is also convenient. Therefore, the proposed output driver is easily able to increasing the equalization gain of CML pre-emphasis output driver without additional power consumption.