I. INTRODUCTION

As the data rate of a serial link increases, it becomes more challenging to compensate for the loss of channel which degrades received signal integrity. At receiver side, continuous-time linear equalizer (CTLE) and/or decision feedback equalizer (DFE) are employed to remove the inter-symbol interference (ISI) due to channel loss^[1,2]. While DFE is effective in removing post-cursor ISI without amplifying noise, it cannot remove pre-cursor ISI and the number of DFE taps may become excessive with long-tail ISI. For this reason, CTLE usually precedes DFE to remove pre- and post-cursor ISI with reasonable number of DFE taps.

The non-zero input offset of CTLE, however, reduces the eye-opening of following sampler and thus the bit-error rate (BER) of clock and data recovery (CDR) circuit. The input offset can be cancelled by extracting the DC component at the output of CTLE and subtract it from its input^[3]. The DC component can be extracted by a low-pass filter (LPF) whose bandwidth (BW) should be low enough not to affect the received signal integrity. This BW requirement easily results in very large values of resistance and capacitance, meaning large silicon area. The input offset of CTLE appears as the difference between the peak signal levels of differential CTLE output. Therefore, the input offset can be detected by a peak detector without LPF occupying large area. A peak detector, however, has to operate at full speed of serial data input and should have negligibly small input offset, which may result in large power consumption^[4]. The input offset can also be cancelled using sampled data in digital domain with pre-defined training input pattern^[5]. With this type of digital offset cancellation, a dynamically varying input offset cannot be removed if without periodical offset cancellation. For offset cancellation in digital domain without any pre-defined training pattern, edge and data samples are used to see if the input offset of CTLE is positive or negative but different input offsets of edge and data samplers cannot be cancelled^[6].

This paper describes an input offset cancelled CTLE for a 12-Gb/s wireline receiver. An offset canceller (OFC) extracts the DC component of the CTLE output and subtracts it from the CTLE input. In order not to affect the received signal integrity, the BW of the OFC is designed to be 10-kHz which is set by an active-RC integrator extracting the DC component of the CTLE output. To realize the 10-kHz BW in a small silicon area, the effective resistance of the active-RC integrator is increased by pulse width modulation (PWM). The input offset of the OFC itself is removed by chopping. Section II describes the architecture and circuit implementation of the offset cancelled CTLE. The experimental results are given in Section III and finally the paper is concluded in Section IV.

II. ARCHITECTURE AND IMPLEMENTATION

The architecture of the 12-Gb/s wireline receiver with an input offset cancelled CTLE is shown in Fig. 1. The channel loss is compensated by the combination of CTLE and three-tap DFE. The phase of the sampling clock and the tap values of the DFE are controlled by the clock and data recovery (CDR) and DFE adaptation logics. The OFC detects the DC component at the CTLE output and feeds it back to the CTLE input where the input offset is subtracted.

Fig. 1. Architecture of a 12-Gb/s wireline receiver with offset cancelled continuous-time linear equalizer (CTLE).

1. Continuous-time Linear Equalizer

The CTLE has three stages of boosting amplifiers (BA) shown in Fig. 2. The cross-coupled nMOS transistors and the capacitor $C_{NC}$ (=0.1-pF) provide negative resistance and capacitance at the output, which widens the BW without consuming large power^[7]. The differential impedance $Z_{NC}$ seen at the output is given as;

Fig. 2. Schematic of the boosting amplifiers (BA) of the CTLE with negative resistance and capacitance (a) BA1 with the feedback input from the OFC, (b) BA2 and BA3.

(1)

$Z_{N C}=-\frac{1}{s C_{N C}}-\frac{2}{g_{m, N C}}$

where $g_{m,NC }$is the transconductance of the cross-coupled nMOS transistors. The boosting gain can be controlled by varying the resistance $R_{S}$, the capacitance $C_{S}$, and the bias current ratio $I_{SS1}$:$I_{SS2}$ as shown in Fig. 3. The sum of the two current sources $I_{SS1}$ and $I_{SS2}$ is 3.2-mA and $I_{SS3}$ is 0.6-mA. As can be seen in the figure, larger boosting gain can be achieved with the negative resistance and capacitance. The resistor $R_{S}$ and the capacitor $C_{S}$ are realized as switchable resistor array and switchable capacitor array, respectively.

Fig. 3. Simulation frequency response of the boosting amplifier.

2. Offset Canceller

In order to cancel the offset of the three-stage CTLE, the DC component of the CTLE output is extracted and fed back to the CTLE input by the OFC as shown in Fig. 1. Because the OFC itself can have non-zero input offset, the chopping amplifier (CHA) is added at the OFC input. To minimize the unwanted amplification of the high frequency component of the CTLE output, a passive LPF consisting of $R _{3}$ and $C _{3}$ with 13-MHz BW precedes the CHA. The CHA output is low pass filtered by $R _{2}$ and $C _{2}$ to remove the up-converted input offset. The frequency of the chopping clock CLKCHOP is chosen to be 10-MHz to have reasonably small values of $R _{2}$ and $C _{2}$. The CHA is designed to have 100-MHz BW with the feed-forward path as shown in Fig. 4(a)^[8]. The DC gain of the CHA is smaller than 30-dB over all corners to prevent the output saturation by its own input DC offset. The cut-off frequency of the LPF formed by $R _{2}$ and $C _{2}$ is 500-kHz which is low enough to remove the up-converted DC input offset.

Fig. 4. Schematics of the (a) chopping amplifier (CHA), (b) operational amplifier (OPA).

The active-RC integrator consisting of the operational amplifier (OPA) shown in Fig. 4(b), $R _{1}$, and $C _{1}$ extracts the DC component of the CTLE output. The extracted DC component is fed back to the first boosting amplifier BA1 shown in Fig. 2(a). Depending on the OFC output proportional to the DC component of the CTLE output, the bias current $I_{SS3}$ is steered differentially to cancel the input offset of the CTLE. The cut-off frequency of the low-pass filtering OFC loop is desired to be 10-kHz to avoid the baseline wandering. To realize the cut-off frequency of 10-kHz with conventional active-RC integrator, the resistance and capacitance values have to be very large, occupying large silicon area. To minimize the required silicon area, the effective resistance of the resistor $R _{1}$ is increased by employing the pulse width modulation (PWM) as shown in Fig. 1. The amount of charge transferred to the capacitor $C _{1}$ per clock cycle is controlled by varying the duty cycle of the clock $CLK_{PWM}$. If the duty cycle of $CLK_{PWM}$ is 50-%, the effective resistance of $R _{1}$ is doubled. In this work, the duty cycle of $CLK_{PWM}$ is set to be 1-%. By employing this PWM technique, the required values of $R _{1}$ and $C _{1}$ to get the desired bandwidth of 10-kHz are reduced from 2.4-MΩ and 7-pF to 240-kΩ and 0.7-pF, respectively and the required silicon area is reduced by 25 times.

3. Sampler

The sampler shown in Fig. 5 has dynamic sense amplifier structure and has additional differential input pair $V_{TAP}$ and $V_{TAPB}$ used for the cancellation of its own input offset. The input offset cancellation of the sampler is performed before the wireline receiver begins its normal operation. During the input offset cancellation of the sampler, the differential data input $V_{INP}$ and $V_{INN}$ are shorted to their common-mode level. The sampler output is monitored for long time to see its DC component. The differential level of the input $V_{TAP}$ and $V_{TAPB}$ is controlled by a simple digital-to-analog converter (DAC) till the sampler output has zero DC component.

Fig. 5. Sampler.

III. EXPERIMENTAL RESULTS

The offset-cancelled CTLE is applied to a 12-Gb/s wireline receiver which is designed to be compliant with the high-definition multimedia interface (HDMI) version 2.1. The 12-Gb/s wireline receiver has four data channels which have separate receiver data paths consisting of an offset-cancelled CTLE, DFE, and CDR. The chip microphotograph of the four-channel 12-Gb/s wireline receiver implemented in a 28-nm CMOS technology is shown in Fig. 6. The silicon area occupied by the OFC is 0.0015-mm².

Fig. 6. Chip microphotograph.

Fig. 7(a) shows the eye diagram at the input of the CTLE when a pseudo-random binary sequence (PRBS) 12-Gb/s input is applied through a channel with 17-dB loss at 6-GHz. The eye is closed due to the ISI resulting from the channel loss and the CTLE re-opens it as shown in Fig. 7(b) and Fig. 7(c). With the OFC disabled, the CTLE output has 45-mV offset as shown in Fig. 7(b), which reduces the sensitivity of the sampler. This offset is completely removed if the OFC is enabled as shown in Fig. 7(c).

Fig. 7. Simulated eye diagram with 12-Gb/s PRBS input (a) at the CTLE input, (b) at the CTLE output with the OFC disabled, (c) at the CTLE output with the OFC enabled.

Fig. 8 shows the measured bit-error rate (BER) when a PRBS 12-Gb/s input is applied through a HDMI cable with 17-dB loss at 6-GHz. Even though the CTLE is operating, the BER is always larger than 10^-12 when the OFC is disabled. With the OFC enabled, the width of eye is larger than 0.26 unit-interval (UI) for the BER smaller than 10^-12.

Fig. 8. Measured bit-error rate (BER) versus the sampling clock position.

The BER of the receiver is measured as a function of the differential input swing as shown in Fig. 9. When the OFC is disabled, the BER is saturated to be 10^-9 for the differential input swing larger than 120-mV. With the OFC enabled, the BER becomes smaller than 10^-12 for the differential input swing larger than 100-mV as shown in the figure.

Fig. 9. Measured input sensitivity of the receiver.

The offset-cancelled three-stage CTLE consumes 21-mW from a 1.0-V supply, meaning 7-mW per gain boosting zero. The performance of the offset-cancelled CTLE is summarized and compared with other works in Table 1.

IV. CONCLUSIONS

The offset of CTLE is cancelled by an analog offset-cancellation loop whose BW is 10-kHz. The effective resistance of the resistor determining the BW of the offset-cancellation loop is increased by PWM technique. This allows the realization of the offset-cancellation loop in a very small silicon area. A 12-Gb/s wireline receiver with the proposed offset-cancelled CTLE has been implemented in a 28-nm CMOS technology. With the proposed offset cancellation loop, the wireline receiver shows improved BER and input sensitivity.