I. INTRODUCTION

Through-silicon via (TSV) -based 2.5D and 3D stacked-integrated circuits (SICs) allow integrating many devices into a single package and result in highperformance devices. A TSV is a vertical metal interconnect that electrically connects two dies through a silicon substrate. In comparison to 2D-ICs, a TSV-based SIC improves the interconnect length, power consumption and on-chip data bandwidth^[1,3].

However, the test complexity and cost of SICs is higher than for 2D-ICs. Unlike 2D-ICs, there are various test stages for SICs, which contribute to the test cost. The test stages for SICs include a pre-bond test of each die, mid-bond or partial-stack test after each stacking, postbond test after complete stacking, post-bond test after complete stacking and the final test after packaging^[4]. Except for the final packaged test, all test stages are performed at the wafer-level. Marinissen et al.^[5] have used a modular test approach for SICs that considers various dies and TSV-based interconnect layers as separate test units. Modular test moreover allows stacking dies from different manufacturers.

A standardization working group for a 3D test (P1838)^[6] has proposed a test access architecture for 3D SICs that supports modular testing. Compatibility with P1838 can be observed in recent research on different issues related to SICs^[7,12]. Besides developments in test equipment have led to a tester-channel frequency beyond 1 GHz^[13], which is underutilized due to increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies^[14].

Therefore, in this paper we aim to reduce the test cost of SICs (2.5D and 3D) by leveraging the tester-channel frequency at both the wafer-level and package-level tests. We present a time-multiplexed test access architecture for SICs that is compatible with IEEE P1838. The proposed architecture accesses multiple dies in a timedivision manner with a higher tester-channel frequency, while respecting (1) the scan-shift frequencies of the cores and (2) test frequency limits imposed by the waferlevel package-level tests. It significantly reduces the absolute the time at each test stage of a SIC. We assume that the pre-bond test on all dies to be stacked is already performed.

The remaining paper is organized as follows. In the following section, we discuss the related work and limitations. In Section III, we present the proposed timemultiplexed test access architecture. The experimental results and an analysis on the test time are given in Sections IV and V, respectively. The paper is concluded in Section VI.

II. RELATED WORK AND LIMITATIONS

The DFT infrastructure of stacks of 1149.1-wrapped dies and 1500-wrapped dies are respectively illustrated in Fig. 1(a) and Fig. 1(b). Each 1149.1-wrapped die has its own TAP controller and its control signals are TMS, TCK and RST (optional). The serial and parallel data input (output) for a SIC with 1149.1-wrapped dies are TDI and PTI (TDO and PTO), respectively. However, for SICs with 1500-wrapped dies, there is a common TAP controller, which generates 1500-wrapper control signals (WCS) along with the serial input (WSI) and output (WSO). The parallel data input and output for 1500-wrapped dies are WPI and WPO, respectively. The above-mentioned test access architecture has some limitations, which are discussed throughout this section.

Fig. 1. Test access architecture with (a) 1149.1-based die wrappers, (b) 1500-based die wrappers.

Generally, besides sequential test access to each die, the test access optimization schemes can result in daisychained and/or parallel accesses^[15,17], as illustrated in Fig. 2. In a daisy-chain connection, the cores of different dies have a common test access mechanism (TAM). However, in a parallel connection, there are separate TAM wires for the cores of different dies. The sequential and daisy-chained accesses to multiple dies offer a full test bandwidth to each die. However, the daisy-chain access increases the number of test I/O pads at the pre-bond test stage and the routing cost, due to different TAMs at the pre-bond and post-bond test stages^[15,16].

Noia et al.^[17] have shown pareto optimality of the die-test time with the 3D TAM width because the test time does not always change with the 3D TAM width. Based on this fact, they have presented a 3D TAM optimization technique, which distributes the 3D TAM wires among multiple dies by constraining the available test pins and TSVs. This allows testing multiple dies in parallel, as shown in Fig. 2(b). However, in [17]^[17], complete stack is considered for optimizing 3D TAM, which may not efficiently improve he test time at each partial-stack stage due to their non-optimal test schedules. Therefore, Noia et al.^[18] have presented optimization methods to support test scheduling for each stage of stacking. The approaches in [17]^[17] and [18]^[18], the size, complexity and tier of each die affect the test time of the stack. Thus, during optimization, information of the number of dies to be stacked and the tier of each die is required.

Fig. 2. General test access schemes for cores of two dies (a) daisy-chain, (b) parallel with distributed TAM wires.

Furthermore, the control signals are broadcast to all die wrappers, which therefore stay in a common state, e.g., shift, capture, update, even though each 1149.1-wrapped die has a separate TAP controller. Therefore, we cannot independently control each die wrapper that may unnecessarily prolong the shift-state of some dies due to a longer shift-state of other die/dies.

Thus, during parallel test of multiple dies, the test time of some cores may increase that potentially increase the test time of the corresponding SIC.

For example, with a stack of two dies, each has the maximum scan chain length and test sequences (Lmax, Tseq), as shown in Fig. 3(a). An optimization evenly distributes eight wires of inter-die TAM to each stackeddie. With this configuration, the test time of the stack with independent and dependent test access to each die wrapper is illustrated in Fig. 3(b) and Fig. 3(c), respectively. With an independent test access, the test operation on both dies do not disturb each other. However, with a dependent test access, the stack is tested in two test sessions, see Fig. 3(c), because the core with the longest scan chain and the fewest test sequences interrupts the test operation on the opposite die core. In Fig. 3(c), (Lmax, Tseq) of each session is mentioned in the reddashed rectangle. It shows that Lmax of core-B is dominant during session 1 and increases the test time of core-A. However, Lmax of core-A is dominant during session 2 and increases the test time of core-C. Ultimately, the test time of the stack is increased with a dependent test access to each stacked die.

Fig. 3. (a) Example stack of two dies and its test time with (b) independent access, (c) dependent access to both die wrappers.

Moreover, a parallel test of multiple dies contributes to the peak scan-shift and capture power and this is not considered during the 3D TAM optimization in [7]^[7], [16]^[16].

III. TIME-MULTIPLEXED TEST ACCESS ARCHITECTURE FOR SICS

This section presents the proposed time-multiplexed test access architecture for SICs, but for simplicity, the entire discussion is based on 3D SICs. In order to leverage the available resources for improving the test cost, TDM has also been applied to the VirtualScan architecture^[19], network-on-chip-based TAM^[20], dynamic voltage-frequency scaling (DVFS)-based systems^[21], IEEE std. 1687 based designs^[14].

Fig. 4 illustrates an example of the proposed timemultiplexed test access architecture for a stack of three dies. Each die wrapper is accessed in a time-division manner with a higher test-channel frequency in this simple yet effective approach. The proposed architecture connects all of the test data and control lines to each die wrapper in parallel, unlike the conventional P1838 architecture. Each die elevates its serial/parallel test data input to the upper die instead of elevating its own output. Each test data output is shifted-out the stack through an inter-die parallel-in serial-out shift register and each of its flip-flop is embedded on different dies. This register loads the test response from die wrapper in parallel with TCK if the parallel load signal (P_Ld) is ‘1’, and serially shifts the loaded test response out the stack, otherwise. The time-muxed-clock circuitry clocks the corresponding die wrapper and controls the flip-flop of the inter-die shift register during the allocated time slot.

Fig. 4. An example of time-multiplexed test access architecture for a three-die stack.

The number of time slots is selected according to the scan-shift frequency of each die and the tester-channel frequency. For example, the stack-under-test has three dies (refer Fig. 4) and the scan-shift frequency for each die is 50 MHz; therefore, the tester-channel frequency of 150 MHz can be used to test the three dies in a timedivision manner. This setup creates three time slots and each time slot is allocated to a single die. Fig. 5 illustrates a timing diagram for this example. It shows three non-overlapping clocks for the three dies. Each die samples the test data that is on a common inter-die TDM in the corresponding time slot. This architecture increases utilization of the tester-channel frequency, which significantly improves the absolute test time of the SIC. Moreover, due to the non-overlapping clock for each die, the peak test power of the stack-under-test is associated to only one die, unlike parallel tests with distributed TAM wires.

Similarly, for example, if the scan-shift frequencies for three stacked dies are 25 MHz, 25 MHz, and 50 MHz, respectively from bottom to top, the tester-channel frequency of 100 MHz can be used to test them in a timedivision manner. Thus, four time slots are created: die 1 and die 2 are allocated the 2nd and 4th time slots, respectively, and die 3 is allocated both the 1st and 3rd time slots, as shown in Fig. 5. Likewise, the number of time slots can be created for the stack-under-test and those can be assigned to the stacked dies.

Fig. 5. Illustration of time-division multiplexing for three stacked dies.

The time-multiplexed test access may impede the diagnosability; therefore, the conventional test access is also important. Therefore, configurability is presented to configure either time-multiplexed test access or the conventional test access, as illustrated in Fig. 6. It has a die wrapped with either IEEE 1149.1 or 1500 standard and multiplexing logic.

Fig. 6. A die equipped with configurable time-multiplexed test access.

The time-muxed-clock circuitry is a configurable block, which generates (1) the desired number of time slots for a specific stack, (2) the TDM_clk pulse at the allocated time slots of the corresponding wrapped-die, and (3) P_Ld signal for inter-die parallel-in serial-out shift register and it is asserted when the counter’s output is ‘00’, i.e., at the end of each cycle of the recursive time slots. The number of time slots for a stack and the allocated time slots for a die are configured via a test data register (refer Fig. 7). Thus, we can configure the number of time slots according to the test stage and the allowed test frequency at the test stage. Moreover, we can allocate certain time slot/slots to a stacked die. This flexibility allows leveraging the upper-limit of the test frequencies at wafer-level as well as at package-level tests; thus, relaxes from the knowledge of the number of dies (even from different manufacturers) to be stacked and the hierarchical tier of each die.

Fig. 7 illustrates an example of a 2-bit configurable time-muxed-clock circuitry (lower block) and TDM test data register (upper block). The time-muxed-clock circuitry is comprised of a comparing logic and a counter, which is negative edge triggered. The size of the counter can be selected based on maximum possible time slots for the SIC, for example, 4-bit counter for 16 possible time slots.

Fig. 7. A 2-bit configurable time-muxed-clock circuitry, which is configured through TDM test data register to generate three time slots (0, 1 and 2) and allocate the 2nd time slot to the corresponding stacked die.

The TDM test data register can be selected with a new instruction. It has four segments: TDM_mode, TDM_clk_EN, No. of time-slots, and Allocated time-slot. The first two segments are single-bit segments, and the length of the remaining segments is same as the size of the counter.

1. The TDM_mode segment configures either convention test or TDM test configuration. It controls all multiplexers and flip-flops of inter-die shift registers illustrated in Fig. 6. If TDM_mode is ‘1’, the TDM test configuration is enabled otherwise conventional test configuration.

2. The TDM_clk_EN segment enables the counter of the time-muxed-clock circuitry if TDM_clk_EN is ‘1’. The counter can be disabled when the test operation of the corresponding die is finished or when it needs to be paused due to the test schedule.

3. The No. of time-slots segment’s contents limit the counting range of the counter of the time-muxed-clock circuitry. In other words, its contents describe the number of time slots during specific test stage. The contents of this register are bit-wise compared with the counter’s output to generate a reset signal for the counter that is a synchronous reset.

4. The Allocated time-slot segment’s contents describe the time slot that is allocated to the corresponding die. These contents are also bit-wise compared with the counter’s output, and if both matches, a TDM_clk pulse is generated. To allocate multiple time slots to a die, multiple Allocated time-slot segments are required.

The example time-muxed-clock circuitry in the figure recursively counts 0, 1 and 2, i.e., generates three time slots, and allocates 2^nd time slot to the corresponding stacked die.

The time-multiplexed test access for SICs of 1149.1-wrapped dies, the TMS signal is connected in parallel to all die wrappers like P1838 architecture. However, due to a non-overlapping TDM-clk for each die, a separate TMS signal can be applied to each die wrapper, which allows independent control of each die wrapper. This can be achieved by merging the TMS signal streams of multiple die wrappers into a single stream. The merging is performed in such a way that each die wrapper samples the corresponding TMS signal during its allocated time slot.

For example, there is a stack of two 1149.1-wrapped dies. The shift-states for the bottom die and top die cores are three cycles and one cycle wide, respectively. The shift state is followed by capture, Exit1-DR, Update-DR and Select-DR-Scan states; each is a single cycle wide. Therefore, the sequence of states for both die wrappers is different and can be implemented with 1149.1-wrapped dies only.

Fig. 8(a) illustrates TMS sequences for both die cores, and those are merged into a single stream. The scan-shift frequency for both dies is same and the tester-channel frequency is two times higher than the scan-shift frequency. Therefore, the period of the merged TMS stream is decreased by two and it is applied to the stackunder-test, where each die wrapper samples a TMS signal during its time slot.

Fig. 8(b) illustrates the timing diagram of two 1149.1-wrapped dies, which are accessed with TDM. The figure shows a non-overlapping TDM_clk for both die wrappers that samples a TMS pulse in a time-division manner. Since both die wrappers receive separate TMS signals, their TAP controllers’ states are independent of each other.

Fig. 8. (a) Merging two streams of TMS signals, (b) timing diagram of two 1149.1 wrapped dies with their wrapper states, during time-multiplexed test access.

However, since there is a common TAP controller for the stack of 1500-wrapped dies, we cannot apply separate wrapper control signals to each die wrapper like the conventional P1838 architecture. Therefore, the period of a TMS signal is extended for the test clock cycles equal to the number of time slots.

Hence, as the proposed architecture accesses multiple dies in a time-division manner with faster tester-channel frequency and with full test bandwidth, the absolute test time is significantly reduced compared to the sequential test of each stacked-die. Moreover, since the timemultiplexed access to each 1149.1-wrapped die allows independent die wrapper control, we can achieve higher reduction in the absolute test time compared to TDM for 1500-wrapped dies.

IV. EXPERIMENTAL RESULTS

In this section, we present an evaluation of the timemultiplexed test access of a synthetic SIC with five SoCs from the ITC’02 benchmark set^[22]. The following five SoCs are stacked respectively from bottom to top, p93791, p34292, p22810, f2126 and d695, and each SoC is considered a separate die. For demonstration, the tier of each SoC is assigned according to their test time, i.e., the SoC with the highest test time is placed at the bottom. We assumed that all cores are soft cores, and all cells (boundary and scan) of a core are evenly distributed among TAM wires, i.e., $\left\lceil\frac{\text {total cells}}{T A M \text { width}}\right\rceil$ , where the TAM width is 16 wires. Cores of an SoC are considered in a single design level rather than hierarchy levels.

For simplicity, we assume that the cores of each SoC are sequentially tested with the full TAM width. The scan-shift frequency is 50 MHz, and the test frequency limits at the wafer-level and package-level tests are 100 MHz and 1 GHz, respectively. Thus, the upper bounds of the number of time slots at the wafer-level and packagelevel tests are 2 and 20, respectively. We have calculated the absolute test time for three test cases: sequential test, TDM with 1500-wrapped dies, and TDM with 1149.1-wrapped dies.

Table 1 presents a comparison of the total absolute test time of the synthetic SIC with the three cases. The first column of the table lists different test stages and the second column specifies the test schedule at each test stage. The third and fourth columns specify the test frequencies and number of time slots at each test stage. The last three columns specify the total absolute test time of the SIC with the three cases.

The results reveal that in the two TDM-based cases total absolute test time of SIC is significantly reduced compared to the sequential test access to each die. Furthermore, TDM with 1149.1-wrapped dies results higher reduction than TDM with 1500-wrapped dies. The major reduction is achieved at the package-level test, which is performed at 250 MHz. Since the test time of all dies is not same, dummy bits are transmitted until all stacked dies are tested. Thus, an efficient scheduling can further improve the test time with the proposed timemultiplexed test access.

V. TEST TIME ANALYSIS OF SICS WITH TDM

This section presents an analysis of the test time of SICs with the TDM-based test access architecture. The analysis is based on the number of time slots and the test frequencies at different test stages. For analyses, only absolute test time is considered because TDM-based test access reduces the absolute test time of SICs rather than the number of test clock cycles. Here, a single time slot is assigned to each stacked die; thus, the number of time slots is same as the number of stacked dies. However, multiple time slots can also be assigned to a single stacked die.

The proposed test access allows the test data register of different stacked dies to be accessed in a time-division manner that can be the scan chain of a core or boundary chain for an inter die interconnect test. Since the scan chains are the major contributor to the total test time of an IC, we do not include the interconnect test time in our calculations in this paper.

We assumed homogeneous known good dies to be stacked and each die has a single core with a single scan chain. The length of the scan chain is 1000 cells and it has 100 test sequences. The number of test clock cycles for a die is (1000+1)×100 = 100100, and its absolute test time, for example with 50 MHz of test frequency, is 100100/50 MHz = 2.002 msec. Since the dies are homogenous, the test time for 1149.1- and 1500-wrapped dies will be same.

The scan-shift frequency is 50 MHz, and the upper limit of wafer-level and package-level test frequencies are 100 MHz and 1 GHz, respectively. Thus, the respective upper bounds of the number of time slots are $\left\lfloor\frac{f_{r}}{f_{s}}\right\rfloor=\left\lfloor\frac{100 M H z}{50 M H z}\right\rfloor= 2$ and $\left\lfloor\frac{f_{r}}{f_{S}}\right\rfloor=\left\lfloor\frac{1 G H z}{50 M H z}\right\rfloor= 20$, where fT and fS represent the tester-channel and scan-shift frequencies, respectively. The total test time of a SIC is the sum of the test times at all its test stages. For example, if three known good dies are stacked into a single SIC, its test stages include:

1) A wafer-level test of a stack of two dies with TDM at 100 MHz; this test can be represented as TDM(1,2).

2) A wafer-level test of a stack of three dies in which two dies are tested with TDM at 100 MHz and, sequentially, on die is tested at 50 MHz. This test can be represented as TDM(1,2),3.

3) A package-level test of packaged stack of three dies in which three dies are tested with TDM at 150 MHz, since package-level test can be performed at higher tester-channel frequency (1 GHz for this analysis). This test can be represented as TDM(1,2,3).

In this example, due to a lower limit of wafer-level test frequency, the test time of the post-bond test of the threedie stack is longer than its packaged test. Since most of the tests of a SIC are performed at wafer-level, a higher wafer-level test frequency limit will result in a shorter test time of the SIC.

By assuming that the upper limit of the wafer-level test frequency may increase in the future, we analyzed the effect of the wafer-level test frequency on the total test time of SICs. We studied the effect with three different frequencies: 100, 150 and 200 MHz. Moreover, we varied the number dies of SICs from 2 to 20. For each case, the upper limit of the package-level test is 1 GHz, and the scan shift frequency is 50 MHz. For simplicity, the test time is normalized from 0 to 1 and is plotted in a clustered bar chart, as shown in Fig. 9. Each cluster of bars is associated with a SIC with a specific number of stacked dies (from 2 to 20). Four bars of each cluster, respectively from left to right, represent the normalized absolute test time with the sequential test, TDM-based tests with wafer-level frequencies of 100, 150 and 200 MHz. In sequential test access, the sum of the test time of all stacked dies is the total test time of a stack.

Fig. 9. Comparison of normalized total absolute test time of different sized SICs, resulting from sequential and TDM-based (with three different wafer-level test frequency limits, W-fT) test accesses.

We can observe from the chart that the test time of each SIC is significantly reduced with the proposed TDM-based test accesses as compared to the sequential test access. Moreover, for a specific number of stacked dies, the increasing wafer-level test frequency limit decreases the test time of the SIC.

Furthermore, with an increasing number of stacked dies, the percentage reduction in the test time with TDM as compared to the sequential test is illustrated in Fig. 10. Each line in the line chart represents the percentage reduction with different wafer-level test frequency limits. The chart shows that the percentage reduction with a wafer-level test frequency limit of 100 MHz remains around 50%, regardless of the number of stacked dies of SICs. However, a higher reduction can be achieved with the wafer-level test frequency limit of 150 and 200 MHz as the number of stacked dies increases. Furthermore, intuitively, a higher package-level test frequency will also decrease the total test time of an SIC. Thus, the proposed time-multiplexed test access architecture for SICs is scalable in terms of the number of stacked dies and test frequency limits at each test stage.

Fig. 10. Percentage reduction in total absolute test time of different-sized SICs with TDM-based (with three different wafer-level test frequency limits, W-fT) test access, as compared to the sequential test access.

VI. CONCLUSION

We have presented a configurable time-multiplexed test access architecture that is compatible with IEEE P1838, for stacked ICs that leverages the tester-channel frequency at both the wafer-level and package-level tests. Its configurability relaxes from the knowledge of the number of dies to be stacked and hierarchical level of each die. The proposed test access architecture is compatible with die wrappers based on IEEE standards 1149.1 and 1500. It is evaluated with a synthetic SIC that is based on five ITC’02 benchmark SoCs. The results showed that the time-multiplexed test access time is significantly reduced with respect to the sequential test access to each die. However, the test time for stack of 1149.1-wrapped dies is the least because each 1149.1-wrapped die has its own TAP controller and allows independent control of each die wrapper, unlike with 1500-wrapped dies. Moreover, the analysis showed that the proposed architecture scales well with the number of stacked dies and the upper test frequency limits at waferlevel and package-level tests.