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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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References

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L. Kull et al., “A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013.DOI
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B. Kim, L. Yan, J. Yoo and H.-J. Yoo, “A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology,” J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32, Jan. 2011.DOI
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Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35- ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC," Dig. Tech. Papers 2015 Symp. on VLSI Circuits, pp. C64-C65.DOI
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Q. Zhang, J. Li, Z. Zhang, K. Wu, N. Ning, and Q. Yu, “A 13b-ENOB third-order noise-shaping SAR ADC using a hybrid errorcontrol structure,” in Dig. Tech. Papers IEEE Custom Integr. Circuits Conf. (CICC), 2021, pp. 1-2.DOI
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T.-H. Wang, R. Wu, V. Gupta, and S. Li, “27.3 A 13.8-ENOB 0.4pF-CIN 3rd-order noise-shaping SAR in a single-amplifier EF-CIFF structure with fully dynamic hardware-reusing kT/C noise cancelation,” in Dig. Tech. Papers IEEE Int. Solid- State Circuits Conf. (ISSCC), 2021, pp. 374-376.DOI
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M. Yousefirad, M. Yavari, “A fully dynamic third-order EF-CIFF noise-shaping SAR ADC with NTF zeros optimization and passive integration,” Int. J. Electron. Commun. 157, 154422 (2022).DOI
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S. Li, B. Qiao, M. Gandara, and N. Sun, “A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure,” in Dig. Tech. Papers IEEE Int. Solid- State Circuits Conf. (ISSCC), Feb. 2018, pp. 234-236, doi: 10.1109/ISSCC.2018.8310270.DOI
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L. Jie, B. Zheng, H.-W. Chen, and M. P. Flynn, “A cascaded noise-shaping SAR architecture for robust order extension,” IEEE J. Solid-State Circuits, vol. 55, no. 12, pp. 3236-3247, Dec. 2020.DOI
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C. Liu and M. Huang, “A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter,” in Dig. Tech. Papers IEEE Int. Solid- State Circuits Conf. (ISSCC), 2017, pp. 466-467.DOI
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L. Jie, B. Zheng, and M. P. Flynn, “A calibration-free time-interleaved fourth-order noise-shaping SAR ADC,” IEEE J. Solid-State Circuits, vol. 54, no. 12, pp. 3386-3395, Dec. 2019.DOI
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C. -C. Chen and C. -C. Hsieh, “A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter,” in Dig. Tech. Papers 2021 IEEE Asian Solid-State Circuits Conference (ASSCC), 2021, pp. 1-3.DOI
14 
T. Xie, T. -H. Wang, Z. Liu and S. Li, “An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique,” IEEE J. Solid-State Circuits, vol. 57, no. 12, pp. 3804-3815, Dec. 2022.DOI
15 
J. Liu, D. Li, Y. Zhong, X. Tang, and N. Sun, “A 250kHz-BW 93dB-SNDR 4th-order noise-shaping SAR using capacitor stacking and dynamic buffering,” in Dig. Tech. Papers IEEE Int. Solid- State Circuits Conf. (ISSCC), 2021, pp. 369-371.DOI
16 
Jae-Hyeon Nam, Sung-Hyun Park, Jin-Yeop Jang, Sang-Gyu Park, “Mismatch-Shaping Scheme for Split-Array Capacitive DACs”, Electronics, Vol. 12, p. 1891, 2023DOI