1. EF-CIFF NS SAR ADC

Fig. 1 and 2 show a block diagram and a timing diagram of the proposed NS-SAR ADC, respectively. The block diagram is drawn in a single-ended form for simplicity, whereas the actual circuit was differential. The proposed NS-SAR ADC consists of an 8-b SAR ADC, and a loop-filter, which consists of an EF path and a CIFF path. As mentioned in Introduction, the NS-SAR ADC utilizes two CDACs, namely the coarse CDAC and the fine CDAC. The coarse CDAC is used to generate 8-b digital outputs through conventional SAR operations, and the fine CDAC is used to generate the residue voltage used by EF and CIFF paths for the noise shaping. The EF path consists of an amplifier ($G_{1}$) and finite impulse response (FIR) filters, and the CIFF path consists of an amplifier ($G_{2}$) and switched capacitors ($C_{F1,2}$ and $C_{INT1,2}$).

In Fig. 1, when the sampling clock $\varnothing _{S}$ is high, the analog input $V_{IN}$ is sampled on the coarse and the fine CDACs using bootstrapped switches. After the sampling, when $\varnothing _{NS}$ becomes high, the residue voltage processed by the EF path is injected into the two CDACs. At the same time, the residue voltage processed by the CIFF path is injected into capacitors $C_{F1}$ and $C_{F2}$. After that, while $\varnothing _{NS}$ is still high, an 8-b SAR conversion takes place with $\varnothing _{COMP}$ operating the comparator. The digital output of the SAR conversion ($D_{OUT}$) is input to the DWA block for the mismatch error shaping for the fine CDAC. When $\varnothing _{FINE}$ becomes high, the DWA output is input to the fine CDAC to generate a new residue voltage. When $\varnothing _{AMP}$ becomes high, V-T-V amplifiers amplify the residue voltage with the gain of $G_{1}$ or $G_{2}$. Finally, $\varnothing _{Reset}$ resets $C_{F1}$ and $C_{F2}$ to make them ready for the next cycle.

Fig. 3(a) shows a detailed block diagram of the EF path used in the proposed NS-SAR ADC. The block diagram is drawn in a single-ended form for simplicity, whereas the actual circuit is differential. It is noted that although Fig. 3(a) is drawn as if $G_{1}$ drives only one FIR filter for simplicity, actually $G_{1}$ drives one more FIR filter, which is connected to the coarse CDAC. Fig. 3(b) shows a detailed timing diagrams of the EF path. In Fig. 3(b), $\varnothing _{VTV1}$ operates every cycle to implement one-cycle delay ($z^{-1}$), while $\varnothing _{VTV2\_ 1}$ and $\varnothing _{VTV2\_ 2}$ operate alternately in a ping-pong fashion to implement two-cycle delay ($z^{-2}$). $\varnothing _{NS},$ $\varnothing _{NS\_ 1}$ and $\varnothing _{NS\_ 2}$ operates in the same manner.

The capacitors $C_{res1}$ and $C_{res2\_ 1\left(2\right)}$ store one-cycle and two-cycle delayed residue voltages. When $\varnothing _{NS}$ goes high, the charge sharing between those capacitors and CDAC occurs, which realize a second-order noise shaping. The residue voltage is amplified by the gain $G_{1}$ to compensate for the attenuation caused by the charge sharing. The NTF of the EF path from these operations can be represented by

where K$_{\mathrm{EF}}$ = C$_{\mathrm{res2}}$/(C$_{\mathrm{DAC}}$ + C$_{\mathrm{res1}}$ + C$_{\mathrm{res2}}$) is the charge sharing factor. $C_{res1}$ is set to $2\times C_{res}$ to implement $2z^{-1}$, and $C_{res2\_ 1}$ and $C_{res2\_ 2}$ are set equal to $C_{res}$. To effectively reduce noise within the bandwidth, NTF zero optimization was applied by optimizing $G_{1}\cdot K_{EF}$ ^[10].

Fig. 4 shows the operation of the CIFF path integrator, which is similar to that of ^[14]. First, the sum of the residue voltage $V_{res}\left[k\right]$ generated by the fine CDAC and the previous integrator output voltage $V_{INT}\left[k\right]$ stored on $C_{F}$ are amplified by a V-T-V converter with a gain of $G_{2}$ and the output is stored by $C_{INT}$ [Fig. 4(a)]. Then, $C_{F}$ is reset during $\varnothing _{Reset}=high$ [Fig. 4(b)]. Finally, when $\varnothing _{NS}$ becomes high, $V_{INT}\left[k+1\right]$ is generated by charge sharing between $C_{INT}$ and $C_{F}.$ $V_{INT}\left[k+1\right]$ from these operations can be represented as

where $K_{INT}=C_{INT}/\left(C_{F}+C_{INT}\right)$ is a charge sharing factor. From this, the following transfer function $H_{CIFF}\left(z\right)$ of the CIFF path can be obtained.

In our design, $G_{2}K_{INT}=1$ was used to realize a lossless integrator with a unit gain.

Fig. 5 depicts the signal flow of the EF-CIFF loop filter of the proposed NS-SAR ADC, which cascades the EF and CIFF paths described above. Note that ``1 - 3K$_{\mathrm{EF}}$'' in Fig. 5 represents the attenuation of the input signal by charge sharing. By using this model, the overall NTF of the proposed NS-SAR ADC can be represented as

The proposed ADC has a third-order NTF by combining the 1st-order noise-shaping of the CIFF with the 2nd-order noise\st{-}shaping of the EF. Fig. 6 shows the NTF of the proposed NS-SAR ADC. The values of the parameters are shown in a box in Fig. 6, and the vertical dashed line represents the bandwidth of the ADC. Note that $G_{1}K_{EF}$ = 0.95 < 1 was used for the NTF zero optimization.In the proposed ADC, the quantization can be performed with just a one-input comparator, not a multi-input comparator that generates additional thermal noise. Because of the open-loop nature of the residue voltage integration, the gain of the amplifier does not need to be large. However, the gain of the amplifier should be controlled tightly. This was achieved by using V-T-V- converter-type amplifiers.

2. Voltage-Time-Voltage Converter

The amplifiers used in the EF and CIFF paths of the proposed NS-SAR ADC are PVT insensitive V-T-V converters similar to that in ^[13]. Fig. 7 shows a schematic of the V-T-V converter used as amplifier $G_{1}.$ That of the V-T-V converter used as $G_{2}$ is similar. $C_{DACP}$ and $C_{DACN}$are the input sampling capacitors equivalent to the total capacitance of the fine CDAC, and $C_{OUT}$ is the capacitor to store the amplified voltage. The current sources were cascode current sources using very low threshold voltage transistors. The V-T-V converter amplifies the voltage in two steps. The first is the V-to-T conversion (V2T) that converts voltage signal into a time domain signal and the second is the T-to-V conversion (T2V) that converts the time-domain signal back into a voltage signal.

Fig. 8 shows waveforms obtained from SPICE-level simulations of the V-T-V converter. When $\varnothing _{PRE}$ is high, $V_{OUTP}$ and $V_{OUTN}$ are charged to $V_{DD},$ $\varnothing _{EN}$ becomes high and the AND gates become ready. Then, when $\varnothing _{START}$ is high, $V_{RESP}$ and $V_{RESN}$ gradually decrease as $I_{DAC}$ current sources discharge $C_{DACP}$ and $C_{DACN}$. When $V_{RESP}$ or $V_{RESN}$ goes below the inverters' switching threshold voltage, TP or TN signal is generated. The time-domain output of the first stage is $T_{IN}$, which is the time difference between the pull up of TP and TN signals. This operation is referred to as V2T, and the conversion equation can be expressed by

When TP and TN close the switches connected to the $I_{OUT}$ current sources, $V_{OUTP}$ and $V_{OUTN}$ begin to go down. When either $V_{OUTP}$ or $V_{OUTN}$ decreases enough to turn on $P_{1}$ or $P_{2}$ transistor, $\varnothing _{EN}$ becomes low. This makes TP or TN low, which, in turn, freezes the output voltages $V_{OUTP}$ and $V_{OUTN}$. This second stage operation is referred to as T2V, and the conversion equation can be expressed by

By combining Eqs. (5) and (6), the gain G of the V-T-V converter can be expressed as

In Eq. (7), it can be observed that the gain of the V-T-V converter depends only of the ratio of the capacitors and the ratio of the current sources. When there is a PVT variation, the currents from current sources or the capacitance of individual capacitors can fluctuate; however, it is expected that the ratio between two matched components do not change very much. Therefore, the V-T-V converter is inherently insensitive to PVT variations and can amplify the voltage by the desired gain without complex calibration.

Fig. 9 shows the gain variation against input voltage and temperature variations of the V-T-V converter in the CIFF path obtained from SPICE-level simulations. The target gain was two. Even if the process, the input voltage, or the temperature changes, the gain variation of the V-T-V converter was less than 4 %.

Fig. 10 shows the SNDR degradation versus amplifier gain variation obtained from behavioral simulations. It was assumed that gains $G_{1}$ and $G_{2}$ change by the same rate. When the thermal noise is not considered, it can be observed that for an amplifier gain variation of 4 %, the resulting SNDR degradation is smaller than 4 dB. In more realistic cases where the thermal noise is included, the SNDR is barely affected by the gain variation. Therefore, a complex gain calibration is not required.

3. Mismatch Shaping

The mismatch between capacitors comprising a CDAC can cause nonlinear distortion in a SAR ADC or a noise-shaped SAR ADC like the one proposed here. The proposed ADC use two CDACs, the coarse CDAC for SAR operation and the fine CDAC for the generation of the residue to be used in the noise-shaping. The performance degradation from the mismatch in the fine CDAC is much severe than the degradation from the mismatch in the coarse CDAC because the fine CDAC is responsible for the generation of the feedback signal used in the noise-shaping.

Table 1 shows the SNDR obtained from behavioral simulations of the proposed ADC including the CDAC mismatch. We can observe that the mismatch of up to 0.5 % in the coarse CDAC has very little effect on the SNDR performance. However, the mismatch in the fine CDAC degrades the SNDR seriously. Even with the 0.5 % mismatch, the SNDR is degraded by about 30 dB.

To reduce the distortion caused by the fine CDAC mismatch, the DWA technique was employed. It should be noted that the use of DWA is possible because all the capacitors in the fine CDAC switches together after a SAR conversion is completed.

Fig. 11 shows the structure of the fine CDAC, which adopts a bridge structure to reduce the total capacitance. Both MSB and LSB sides have 4-b resolution. All of the capacitors are designed to have the same unit capacitance$.$ The DWA is applied separately within MSB or LSB sides. Because the effective capacitance of the LSB side seen at the CDAC output is much smaller than that of the MSB sides, the effect of the mismatch in the LSB side to the system performance is much smaller than that in the MSB sides. The behavioral simulation results in Table 1 confirms that. The performance obtained applying the DWA to both MSB and LSB sides is almost identical to that obtained applying DWA to the MSB side only. Therefore, mismatch shaping is applied only to the MSB side for power efficiency.

Fig. 12 shows the output spectrum of the proposed ADC without and with mismatch shaping obtained by MATLAB behavioral simulations. In the simulations, 1 % (standard deviation) was used as the mismatch between unit capacitors, and the mismatch shaping was applied only to the MSB cap array of the fine CDAC. The spectrum in Fig. 12 represents an average of 100 simulations. In Fig. 12, when mismatch shaping is not applied, large harmonic distortion is generated due to mismatch, but when mismatch shaping is applied, the harmonic distortion is significantly reduced by the DWA technique. The residual harmonics after DWA application is mainly even-order ones, which are from the mismatch between sub-arrays responsible for up and down switching of the CDAC ^[16]. This can be further suppressed by using the two sub-arrays alternately in successive conversions ^[16]. However, this scheme was not applied in this work.