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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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  4. 10.5573/JSTS.2024.24.3.284
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References

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K.-D. Hwang, et al, “A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Applications,” in ISSCC, Dig. Tech. Papers, Feb. 2018, pp. 210-211.DOI
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C.-H. Kye, et al, “A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test,” in A-SSCC, Dig. Tech. Papers, Nov. 2022, pp. 6-8.DOI
3 
Y. Song, et al, “A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO,” IEEE Trans. on Circuits Syst. II, Exp. Briefs, vol. 69, no. 3, pp. 759-763, Mar. 2022.DOI
4 
A. Goel, et al, “A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO,” in VLSI-C, Dig. Tech. Papers, Jun. 2010, pp. 141-142.DOI
5 
K. Raczkowski, et al, “A 9.2–12.7GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter,” IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1203-1213, Mar. 2015.DOI
6 
M. Raj, et al, “A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET,” in VLSI-C, Dig. Tech. Papers, Jun. 2017, pp. 182-183.DOI