I. INTRODUCTION

When mass-producing DRAM, interface testing operates at speeds higher than the product’s maximum to ensure reliability. The test frequency developed up to 12 GHz for next-generation graphics double data rate 6 (GDDR6) DRAM. In the previous research ^[1], an on-chip frequency doubler in GDDR6 DRAM generated a high-frequency write clock (WCK) internally, utilizing a low-frequency clock received from the automatic test equipment (ATE). Here, the circuitry of the frequency doubler and clock buffer consumes a lot of clocking power. A recent study proposed a built-out tester (BOT) that reduces the power consumption of DRAM and the cost of ATE by employing the tester outside DRAM and sharing the test board ^[2]. For the GDDR6 DRAM test, the industry has recently adopted the BOT system with a commercial XOR chip which generates differential WCK, a reference clock for data reads and writes in GDDR6 DRAM. Although the XOR chip can be used as a frequency doubler, the duty and jitter characteristics of the WCK are significantly degraded because of the low performance of the XOR chip and the path mismatch of the board trace. The phase-locked loop (PLL) has been the solution as a clock driver in memory systems, cleaning out high-frequency noise in the overall clock distribution path ^[3]. Therefore, a frequency multiplier using a PLL can replace the XOR, as shown in Fig. 1.

Fig. 1. Proposed built-out memory test system replacing XOR with a PLL-based clock driver.

In this letter, we propose a 4.5-to-14 GHz PLL-based clock driver designed to support the wide frequency range of WCK. This work introduces 3-shaped LC-VCOs, a strategy devised to overcome the inherent narrow tuning range of LC-VCOs with optimized capacitor array. In addition, we propose an output common mode control with an 8-bit one-hot code-controlled resistor to support the programmability of the received clock input crossing point for the GDDR6 DRAM test.

Section II shows the circuit description of this work. Sections III and IV show the measurement results and the conclusion, respectively.

II. CIRCUIT DESCRIPTION

The overall architecture to support WCK from DC-to-14 GHz is illustrated in Fig. 2. In low-frequency mode (DC-to-4.5 GHz), ATE signal is directly delivered to GDDR6 DRAM through the buffer and the driver of the BOT. In high-frequency mode (4.5-to-14 GHz), we employ PLL with LC-VCOs to support wide-range and decent jitter performance. Even though LC-VCO has better phase noise than the ring-VCO, its frequency tuning range is narrow. As the C$_{\mathrm{max}}$/C$_{\mathrm{min}}$ ratio for high-Q varactors is limited in a typical CMOS process, the LC-VCO requires at least two values for tank L to achieve a wide frequency tuning range (FTR). Although the coupling LC tank relaxes the overhead of the separate multi-LC tanks ^[4], coupling LC tank may result in an unexpected resonant behavior. Therefore, we employ three isolated LC tanks, placing the spiral inductors of the oscillators far apart to avoid the coupling between them (Fig. 3). Three LC tanks (VCO1, VCO2, and VCO3) cover 16 frequency bands each, which are mode-switched externally by mode selection code. Each VCO is realized with a center-tapped symmetric spiral inductor, MOS varactors, 4-bit MOM capacitor array, and negative G$_{\mathrm{m}}$ cells. Reducing the parasitic resistance of the differential output nodes enhances both phase noise and the Q-factor. Consequently, we aggregate the capacitor network, switch, and G$_{\mathrm{m}}$ cells between the differential output nodes to minimize the parasitic resistance. Table 1 summarizes the designed inductor Q-factor and power consumption of each LC-VCO. The MOM capacitor array tunes the frequency coarsely, covering 16 frequency bands. The MOS capacitor varactors finely tune the frequency with the charge pump voltage. From the post-layout simulation, the free-running FTR of the LC-VCOs covers from 3.7-to-14.7 GHz (Fig. 4). A considerable frequency overlap when switching capacitors ensures continuous frequency tuning in the face of process variation.

Fig. 2. Overall architecture of proposed PLL-based clock driver.

Fig. 3. Circuit implementation and layout floorplan of each LC-VCO.

Fig. 4. Frequency tuning range of each LC-VCO.

The differential WCK transmission line and the termination of the GDDR6 DRAM are 50 ${\Omega}$ impedance for high-speed signaling. As the termination level of the V$_{DDQ}$ at the receiving GDDR6 DRAM is adjusted during the testing, the common mode level (V$_{CM}$) of the transmitting WCK needs to be controllable. This work provides programmability of the clock input crossing point of the GDDR6 DRAM. The test evaluation range is 180 mV centered at 0.7${\cdot}$V$_{DDQ}$. Therefore, we employ a current-mode logic (CML) type output driver for 50 ${\Omega}$ impedance matching and V$_{CM}$ control as shown in Fig. 5. The V$_{CM}$ of WCK is controllable through an 8-bit one-hot code-controlled resistor adjusting the V$_{DDQ,TERM}$. The V$_{DDQ,TERM}$ is expressed as

where R$_{EQ,n}$ = R$_{ON}$|| R$_{n}$ (n = 1 ~ 7). The values of R$_{ON}$ and R$_{n}$ are set to linearize the change of the V$_{CM}$. The V$_{CM}$ changes 25 mV per code in this design. Consequently, the peak-to-peak variation of V$_{CM}$ is 200 mV by measurement. 10 pF capacitor suppresses the supply noise. The tail current source controls the output amplitude, resulting in a maximum amplitude of 190~mV$_{\mathrm{pp,diff}}$ at 14 GHz.

III. MEASUREMENT RESULTS

This work was fabricated in a 40 nm CMOS technology. Fig. 6 shows the chip photomicrograph and measurement setup. The total active area is 0.22 mm$^{2}$. The input differential CLK signal is provided by a CLK source converted with balun and bias tee, while the WCK phase noise is measured by a spectrum analyzer. In this test, we adopt a quad flat no-lead (QFN) package for low cost. The packaged prototype is mounted with the socket in the GDDR6 DRAM test board.

Fig. 5. Proposed CML driver with common mode level control.

Fig. 6. Chip photomicrograph and measurement setup.

Fig. 7. Measured WCK output eye diagrams (upper: input, lower: output) of various frequencies.

Fig. 8. Measured WCK output spectrum at 7 GHz, 11 GHz, and 14 GHz.

Fig. 7 shows the measured input (upper) and WCK output (lower) eye diagrams to verify the frequency range of the BOT. The measured FTR of the PLL is from 4.5-to-14 GHz (FTR = 102.7 %). Fig. 8 shows the measured WCK output spectrum. The measured integrated RMS jitter from 10 kHz to 100 MHz is 129 fs$_{\mathrm{rms}}$, 180 fs$_{\mathrm{rms}}$, and 365 fs$_{\mathrm{rms}}$ at 7 GHz, 11 GHz, and 14 GHz, respectively. The measured phase noise at 1 MHz offset is -123 dBc/Hz, -120 dBc/Hz, and -106 dBc/Hz at 7 GHz, 11 GHz, and 14 GHz, respectively. Table 2 shows a performance summary and comparison results. This work exhibits the best FTR and FoM among the prior-art wide-range LC-PLLs.

IV. CONCLUSIONS

We propose a 4.5-to-14 GHz PLL-based clock driver with wide-range 3-shaped LC-VCOs for the GDDR6 DRAM test. We employ 3 LC-VCOs with an optimized capacitor array to improve phase noise over a wide frequency tuning range. The output common mode level is programmable to support the variation of the clock input crossing point of the GDDR6 DRAM. According to the measurement results, the presented PLL-based clock driver operates from 4.5-to-14 GHz. The resulting BOT system provides wide-range and low-jitter WCK to GDDR6 DRAM, overcoming the limitation of XOR and reducing the test cost of the ATE.