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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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References

1 
C. Wang et al., "Computing-in-memory paradigm based on STT-MRAM with synergetic read/write-like modes," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May. 2021, pp. 1-5.DOI
2 
S. Jain et al., "Computing in memory with spin-transfer torque magnetic RAM," IEEE Trans, Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 3, pp. 470-483, Mar. 2018.DOI
3 
T. Na, “Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), 2023.DOI
4 
Z. He et al., "Exploring STT-MRAM based in-memory computing paradigm with application of image edge extraction," In 2017 IEEE International Conference on Computer Design (ICCD)., Nov. 2017, pp. 439-446.DOI
5 
H. S. Stone, "A logic-in-memory computer," IEEE Trans. Comput., Vol. C-19, no. 1, pp. 73-78, Jan. 1970.DOI
6 
T. Na et al., “STT-MRAM sensing: a review,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 1, pp. 12-18, Jan. 2021.DOI
7 
M. Zabihi et al. "In-memory processing on the spintronic CRAM: From hardware design to application mapping," IEEE Trans. Comput., Vol. 68, no. 8, pp. 1159-1173, Aug 2019.DOI
8 
D. Apalkov et al. "Spin-transfer torque magnetic random access memory (STT-MRAM)," ACM Journal. Emerging Technologies in Computing Systems (JETC), Vol. 9, no. 2, pp. 1-35, May 2013.DOI
9 
R. Bishnoi et al. "Improving write performance for STT-MRAM," IEEE Trans. Magn., vol. 52, no. 8, pp. 1-11, Aug 2016.DOI
10 
L. Zhang et al. "Addressing the thermal issues of STT-MRAM from compact modeling to design techniques," IEEE Trans. Nanotechnology., Vol. 17, no. 2, pp. 345-352, Mar 2018.DOI
11 
C. Wang et al. "Design of an area-efficient computing in memory platform based on STT-MRAM," IEEE Trans. Magn., vol. 57, no. 2, pp. 1-4, Feb. 2021.DOI
12 
G. Patrigeon et al. "Design and evaluation of a 28-nm FD-SOI STT-MRAM for ultra-low power microcontrollers," IEEE Trans. Magn., vol. 7, no. 9, pp. 4982-4987, Sep. 2019.DOI
13 
S. Angizi et al "Design and evaluation of a spintronic in-memory processing platform for nonvolatile data encryption," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 37, no. 9, pp. 1788-1801, Sep. 2018.DOI
14 
H. Yu et al. "An adder using charge sharing and its application in DRAMs," In Proceedings 2000 International Conference on Computer Design, Sep. 2000.DOI
15 
V. Vijay et al. "A Review On N-Bit Ripple-Carry Adder Carry-Select Adder And Carry-Skip Adder," Journal of VLSI circuits and systems., vol. 4, no. 01, pp. 27-32, Mar. 2022.DOI
16 
J.-G. Zhu et al. "Magnetic tunnel junctions," Mater. today., vol. 9, no. 11, pp. 36-45, Nov. 2006.DOI
17 
M. Hosomi et al. "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM," in IEDM Tech. Dig., Dec. 2005, pp. 459-462.DOI
18 
Y. Luo et al. "A variation robust inference engine based on STT-MRAM with parallel read-out," Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) Oct. 2020.DOI
19 
S. Ikeda et al. "Magnetic tunnel junctions for spintronic memories and beyond," IEEE Trans. Electron Devices., vol. 54, no. 5, pp. 991-1002, May. 2007.DOI
20 
M. Zabihi et al. "Using spin-hall mtjs to build an energy-efficient in-memory computation platform," Proc. 20th Int. Symp. Qual. Electron. Design (ISQED), Mar. 2019, pp. 52-57.DOI
21 
E. Deng et al. "Low power magnetic full-adder based on spin transfer torque MRAM," IEEE trans. Magn., vol. 49, no. 9, pp. 4982-4987, Sep. 2013.DOI
22 
S. Lim et al "Highly independent MTJ-based PUF system using diode-connected transistor and two-step postprocessing for improved response stability," IEEE Trans. Inf. Forensics Security., vol. 15, pp. 2798-2807, 2020.DOI
23 
W. Zhao et al "Design considerations and strategies for high-reliable STT-MRAM," Microelectron. Rel., vol. 51, no. 9, pp. 1454-1458, Sep. 2011.DOI
24 
G. P. Devaraj et al "Design and Analysis of Modified Pre-Charge Sensing Circuit for STT-MRAM," 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV), March. 2021, pp. 507-511.DOI
25 
T. Na et al "Comparative study of various latch-type sense amplifiers," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 2, pp. 425-429, Feb. 2014.DOI
26 
B. Wicht et al. "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE Journal of Solid-State Circuit. (JSSC), vol. 39, no. 7, pp. 1148-1158, July. 2004.DOI
27 
T. Na et al., "Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65 nm CMOS", IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 496-504, Feb. 2017.DOI
28 
Q. Dong et al., "A 1-Mb 28-nm 1T1MTJ STT-MRAM with single-cap offset-cancelled sense amplifier and in situ self-write-termination", IEEE J. Solid-State Circuits, vol. 54, no. 1, pp. 231-239, Jan. 2019.DOI
29 
T. Na et al., "Offset-canceling single-ended sensing scheme with one-bit-line precharge architecture for resistive nonvolatile memory in 65-nm CMOS", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 11, pp. 2548-2555, Nov. 2019.DOI
30 
J. Kim et al., "A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM)", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 181-186, Jan. 2012.DOI
31 
F. Ren et al., "A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)", Proc. Int. Symp. Quality Electron Design (ISQED), pp. 275-282, 2012.DOI
32 
P. Chakali et al "Design of High Speed Kogge-Stone Based Carry Select Adder," International Journal of Emerging Science and Engineering. (IJESE), vol. 1, no. 4, pp. 2319-6378, Feb. 2013.URL
33 
R. Anjana et al "Implementation of Vedic mutiplier using Kogge Stone adder," IEEE Int. Conf. on Embedded Sys., July. 2014, pp. 28-31.DOI
34 
T. Brächer and P. Pirro "An analog magnon adder for all-magnonic neurons," J. Appl. Phys., vol. 124, no. 15, Oct. 2018.DOI