| Title |
High-performance Sum Operation with Charge Saving and Sharing Circuit for MRAM-based In-memory Computing |
| Authors |
(Jangseok Yu);(Geonwoo Lee);(Taehui Na) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.2.111 |
| Keywords |
Charge saving and sharing circuit; in-memory computing; full adder; MRAM |
| Abstract |
In the era of big data, Von Neumann architectures, with their separation of processor and memory, face limitations in terms of bandwidth and data movement overhead. MRAM-based in-memory computing (IMC) is a promising approach to address these issues, leveraging MRAM to perform simple logical operations directly within memory. However, implementation of n-bit full adder (FA) using pre-charge sense amplifier requires “n + 1” stages. Although carry lookahead adders can reduce the number of stages, it causes significant area overhead, which makes them unsuitable for IMC applications. Therefore, it is important to explore alternatives that can minimize the number of stages. In this paper, we propose a high-performance multi-bit FA utilizing a charge saving and sharing (CSS) circuit that acquires a carry every 4 bits and performs a sum operation every 4 bits in parallel. The CSS circuit-based FA reduces the number of stages to “n/4 + 5”, while minimizing the associated area overhead. |