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References

1 
O. Villa et al., "Scaling the Power Wall: A Path to Exascale," SC '14: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2014, pp. 830-841, doi: 10.1109/SC.2014.73.DOI
2 
Wulf, Wm A., and Sally A. McKee. "Hitting the memory wall: Implications of the obvious." ACM SIGARCH computer architecture news 23.1 (1995): 20-24.URL
3 
Machanick, Philip. "Approaches to addressing the memory wall." School of IT and Electrical Engineering, University of Queensland (2002).URL
4 
Wilkes, Maurice V. "The memory wall and the CMOS end-point." ACM SIGARCH Computer Architecture News 23.4 (1995): 4-6.URL
5 
Saulsbury, Ashley, Fong Pong, and Andreas Nowatzyk. "Missing the memory wall: The case for processor/memory integration." ACM SIGARCH Computer Architecture News 24.2 (1996): 90-101.DOI
6 
Keckler, Stephen W., et al. "GPUs and the future of parallel computing." IEEE micro 31.5 (2011): 7-17.DOI
7 
Ghose, Saugata, et al. "A workload and programming ease driven perspective of processing-in-memory." arXiv preprint arXiv:1907.12947 (2019).DOI
8 
Ahn, Junwhan, et al. "A scalable processing-in-memory accelerator for parallel graph processing." Proceedings of the 42nd Annual International Symposium on Computer Architecture. 2015.DOI
9 
Ahn, Junwhan, et al. "PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture." 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2015.DOI
10 
Chi, Ping, et al. "Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory." ACM SIGARCH Computer Architecture News 44.3 (2016): 27-39.DOI
11 
B. Yan et al., "RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation," 2019 Symposium on VLSI Technology, 2019, pp. T86-T87, doi: 10.23919/VLSIT.2019.8776485DOI
12 
Yan, Bonan, et al. "Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives." Advanced Intelligent Systems 1.7 (2019): 1900068.DOI
13 
Edelstein, D., et al. "A 14 nm embedded stt-mram cmos technology." 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020.DOI
14 
Ito, Satoru, et al. "ReRAM technologies for embedded memory and further applications." 2018 IEEE International Memory Workshop (IMW). IEEE, 2018.DOI
15 
Mochida, Reiji, et al. "A 4M synapses integrated analog ReRAM based 66.5 TOPS/W neural-network processor with cell current controlled writing and flexible network architecture." 2018 IEEE Symposium on VLSI Technology. IEEE, 2018.DOI
16 
Min-Woo Kwon, Myung-Hyun Baek, Sungmin Hwang, "Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation", Journal of Applied Physics 124, 152107 (2018)DOI
17 
Lee, Junhyeong, Misun Cha, and Min-Woo Kwon. "Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor." Applied Sciences 13.4 (2023): 2628.DOI