Mobile QR Code QR CODE


J. Silva, U. Moon, J. Steensguqrd, and G. C. Temes, “Wide band low distortion delta-sigma ADC topology,” IEE Electron. Lett., vol. 37, no.12, pp. 737-738, Jun. 2001.URL
K. Cho, Y. Kwak, H. Kim, and G. Ahn, “A 101dB dynamic range, 2kHz bandwidth delta-sigma modulator with a modified feedforward architecture,” IEICE Electron. Exp., vol. 15, no. 21, 2018, Art. no. 20180848.DOI
Y. -J. Kim, H. -C. Choi, G. -C. Ahn and S. -H. Lee, "A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp," in IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 620-628, March 2010.DOI
M. S. Akter, R. Sehgal, F. van der Goes, K. A. A. Makinwa and K. Bult, "A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier," in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2939-2950, Oct. 2018.DOI
J. -H. Boo et al., "A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1197-1206, April 2021.DOI
V. Shirmohammadli, A. Saberkari, H. Martinez-Garcia and E. Alarcón-Cot, "Low power output-capacitorless class-AB CMOS LDO regulator," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 1-4.DOI
J. Han, K. Cho, H. Kim, J. Boo, J. Kim, and G. Ahn, “A 96dB dynamic range 2kHz bandwidth 2nd order delta-sigma modulator using modified feed-forward architecture with delayed feedback,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 5, pp. 1645-1649, May 2021.DOI
R. Hogervorst, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," in IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1505-1513, Dec. 1994.DOI
B. Park, C. Han and N. Maghari, "Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal Feedforward," 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Republic of, 2021, pp. 1-3.DOI
J. -S. Park,, "A 12b 100MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs," J. Semicoductor Technology and Science (JSTS), vol. 14, no. 2, pp. 189-197, Apr. 2014.URL
T. -An,, "A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch," J. Semicoductor Technology and Science (JSTS), vol. 17, no. 5, pp. 636-647, Oct. 2017.URL
M. Maruyama, S. Taguchi, M. Yamanoue and K. Iizuka, "A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise," 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, China, 2015, pp. 1-4.DOI
C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996.URL
J. -S. Kim, T. -I. Kwon, G. -C. Ahn, Y. -G. Kim and J. -K. Kwon, "A ΔΣ ADC using 4-bit SAR type quantizer for audio applications," 2011 International SoC Design Conference, Jeju, Korea (South), 2011, pp. 73-75.DOI
J. Huang and P. P. Mercier, "A −105dB THD 88dB-SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation," 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020, pp. 1-2.DOI
J. Kim, Q. Duan, J. Choi, C. Song and J. Roh, "A 2.16-μW Low-Power Continuous-Time Delta-Sigma Modulator With Improved-Linearity Gm for Wearable ECG Application," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4223-4227, Nov. 2022.DOI
L. Meng et al., "A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC," in IEEE Journal of Solid-State Circuits, vol. 58, no. 6, pp. 1636-1645, June 2023.DOI