YuByeong-Ho1
BooJun-Ho1
LimJae-Geun1
KimHyoung-Jung1
LeeJae-Hyuk1
AhnGil-Cho1
-
(Department of Electronic Engineering, Sogang University, Seoul 04107, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Analog-to-digital converter (ADC), class-AB op-amp, delta-sigma modulator, feed-forward (FF), successive approximation register (SAR)
I. INTRODUCTION
Expansion of battery-powered portable devices has prompted the need to reduce power
consumption of delta-sigma analog-to-digital converters (ADCs), which have been widely
used in mobile sensor interfaces due to their high resolution and power efficiency
achieved by noise shaping and oversampling. Using input feed-forward (FF) [1] is a widely used approach to reduce power consumption of the delta-sigma ADC. This
approach makes the loop filter address quantization noise only. Consequently, the
requirement for the analog circuitry is relaxed, resulting in a reduction in power
consumption. Furthermore, in [2], the removal of the internal FF path reduces the current consumed by the first integrator,
as it no longer drives the sampling capacitor of the quantizer. Despite these architectural
efforts, reducing the power consumption of the modulator remains challenging. The
main bottleneck lies in the fact that the op-amp of the loop filter must drive large
capacitors that satisfy the kT / C noise requirement within a given clock period.
The Class-AB op-amp is one of the suitable solutions to deal with this difficulty.
It consumes dynamic current through push-pull operation during slewing and wastes
only a small amount of quiescent current during settling. Therefore, the average current
is reduced. This property makes it well-suited for low power applications [3-6].
This work proposes a discrete-time (DT) 2$^{\mathrm{nd}}$ order delta-sigma modulator
achieving a dynamic range (DR) of 97.7 dB at a 1 kHz bandwidth while consuming a power
of 12.3 ${\mu}$W. The architecture of the modulator is based on a previously proposed
work, which employs modified FF structure with delayed feedback [7]. The proposed ADC adopts a class-AB op-amp [8] for the first integrator to reduce average current and enhance the slew rate. The
architecture of the prototype ADC is discussed in Section II. Detailed implementation
of the op-amp and the ADC is discussed in Section III. The measured results of the
prototype ADC are summarized in Section IV. Finally, a brief conclusion is discussed
in Section V.
II. ARCHITECTURE
Fig. 1 illustrates the z-domain block diagram of the proposed ADC. It consists of two integrators,
a 4-bit asynchronous type successive approximation register (SAR) ADC that incorporates
a passive switched capacitor (SC) adder, as well as digital circuitry including a
clock generator, a dynamic weight averaging (DWA), and a binary-to-thermometer decoder.
A delay of one clock period is inserted in the feedback path to relax the timing constraints
of the modulator [7]. Output of the modulator, Do(z), and input of the first integrator, L(z), is given
by
where U(z) and Q(z) indicate the input of the modulator and quantization noise, respectively.
It can be observed that the delay in the feedback path introduces non-ideal characteristics
even though the noise transfer function, NTF(z), is not affect. Firstly, the signal
transfer function, STF(z), becomes frequency dependent as depicted in (2). Secondly, (4) shows that the loop filter processes a third-order shaped input, whereas that of
a conventional FF modulator only handles quantization noise. However, these non-ideal
properties can be suppressed by employing a decimation filter and an anti-aliasing
filter (AAF) with a sufficient oversampling ratio (OSR). The out-of-band signal amplified
by the STF(z), which is folded back to in band after the down-sampling, can be effectively
mitigated using a low-order decimation filter if the OSR is large enough. Moreover,
the AAF allows the first integrator to deal with only a negligible amount of the out-of-band
input.
Fig. 1. Block diagram of the proposed modulator.
III. CIRCUIT IMPLEMENTATION
1. Fully Differential Class AB Op-Amp
To efficiently drive the 6 pF feedback capacitor of the first integrator and 500 fF
sampling capacitor of the second integrator, which are chosen to meet the kT / C noise
requirement, a class-AB op-amp is utilized for the first integrator. The class-AB
op-amp charges or discharges the loading capacitor by push-pull operation during slewing
while spending optimized current. During the settling period, it consumes only a small
amount of quiescent current. Consequently, employing the class-AB op-amp can result
in reduced power consumption compared to the class-A op-amp, which draws static current
during both the slewing and settling periods. To implement class-AB operation, this
work uses the floating class-AB control [8].
Fig. 2 illustrates a rail-to-rail output stage with a floating class-AB control. The floating
class-AB control transistors M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$ are biased by
stacked diode connected transistors, M$_{\mathrm{B1}}$-M$_{\mathrm{B4}}$. When in-phase
current I$_{\mathrm{IN1}}$ and I$_{\mathrm{IN2}}$ are pushed to control transistors
M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$, the V$_{\mathrm{SP}}$ and V$_{\mathrm{SN}}$
voltages get raised while the difference between these two voltages remains constant.
So that the loaded capacitor of the output node is discharged. Conversely, when I$_{\mathrm{IN1}}$
and I$_{\mathrm{IN2}}$ are pulled from M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$, the
V$_{\mathrm{SP}}$ and V$_{\mathrm{SN}}$ voltages go down, and the loaded capacitor
is charged. This push-pull operation continues until the drain current of M$_{\mathrm{C1}}$
matches I$_{1}$.
Fig. 3 is a schematic diagram of the two-stage op-amp used in the first integrator. The
first stage adopts folded-cascode topology to achieve sufficient DC gain. The input
PMOS devices M$_{1}$ and M$_{2}$, operate at sub-threshold region for better noise
performance [12]. The floating class-AB control is implemented using the transistors M$_{9}$-M$_{12}$.
The noise and the offset of the class-AB control transistors can be simply mitigated
by shifting these transistors into the summing circuit of the first stage op-amp [8]. Then, noise and offset of the op-amp are mainly determined by the first stage op-amp.
M$_{21}$-M$_{28}$form inverting amplifiers for common-mode feedback (CMFB) operation
which will be discussed in subsequent discussion.
Typically, a fully differential multi-stage op-amp employs CMFB at each stage [9-11]. However, using the floating class-AB control scheme with such CMFB is not eligible
as the output stage consist of push-pull transistors operating in a pseudo differential
manner. In this design, a single CMFB with a global feedback loop is utilized, which
senses the output common at the class-AB second stage output and controls current
source of the class-A first stage [3]. As depicted in Fig. 4, the global loop CMFB comprises two common-mode control paths that generate the current
control voltages for the upper and lower sides (V$_{\mathrm{CMFBU}}$ and V$_{\mathrm{CMFBL}}$).
Each path consists of a SC CMFB circuit, an inverting amplifier, and floating current
sources for upper and lower side common-mode control.
The SC CMFBs sense the output common of the op-amp and generate control voltages V$_{\mathrm{CML}}$
and V$_{\mathrm{CMU}}$, which move in the same direction as the output common mode
with a level shifting operation. Then, the common-mode control voltages V$_{\mathrm{CMFBL}}$
and V$_{\mathrm{CMFBU}}$, are generated by inverting V$_{\mathrm{CML}}$ and V$_{\mathrm{CMU}}$
for negative feedback. Subsequently, V$_{\mathrm{CMFBL}}$ and V$_{\mathrm{CMFBU}}$
adjust the output common by controlling floating current sources.
A schematic diagram of the inverting amplifier is shown in Fig. 5. The inverting amplifier for the NMOS current sources consists of M$_{\mathrm{N1}}$,
M$_{\mathrm{N2}}$, and M$_{\mathrm{N3}}$, while the inverting amplifier for the PMOS
current sources comprises M$_{\mathrm{P1}}$, M$_{\mathrm{P2}}$, and M$_{\mathrm{P3}}$.
If the output impedance of the current source (I$_{\mathrm{N}}$, I$_{\mathrm{P}}$)
is sufficiently large, gain of the amplifier, A$_{CMFB}$ is given by
where g$_{M}$$_{\mathrm{N1,}}$$_{M}$$_{\mathrm{P1}}$represents the transconductance
of M$_{\mathrm{N1}}$, and M$_{\mathrm{P1}}$, while g$_{M}$$_{\mathrm{N2}}$, $_{M}$$_{\mathrm{P2}}$
indicates the transconductance of M$_{\mathrm{N2}}$and M$_{\mathrm{P2}}$. Eq. (5) suggests that the settling speed and stability of the output common mode can be adjusted
by controlling the transconductance ratio. In this work, a gain of - 1 / 3 is chosen
to ensure the stable convergence of the output common mode.
Fig. 2. Schematic diagram of the rail-to-rail output stage with a floating class-AB control.
Fig. 3. Schematic diagram of the two-stage op-amp used in the first integrator.
Fig. 4. Block diagram of the global loop CMFB.
Fig. 5. Inverting amplifier of the global loop CMFB.
2. Loop Filter
Fig. 6 illustrates the first integrator of the loop filter. Bootstrapping switch is incorporated
to enhance linearity of the sampling network. In order to mitigate the 1/f noise and
offset, chopper stabilization (CHS) [13] is employed. The class-AB op-amp discussed in the previous section is adopted to
improve power efficiency.
The transfer function of the second integrator, (2 - z$^{-1}$) / (1 - z$^{-1}$), is
implemented as shown in Fig. 7. It samples the first integrator output on the C$_{\mathrm{S2}}$ during the ${\phi}$
$_{\mathbf{2}}$ phase. In the following ${\phi}$ $_{\mathbf{1}}$ phase, the output
of the first integrator is connected to the C$_{\mathrm{S2A}}$ as well as the C$_{\mathrm{S2}}$
and integrated without delay.
Given that the integrator only needs to drive a feedback capacitor C$_{\mathrm{F2}}$,
which is 250 fF, and 80 fF sampling capacitor of the quantizer, using a class-AB op-amp
may not be highly efficient. This is due to the fact that employing a class-AB op-amp
would require additional biasing branches and control circuits. Hence, a simple folded-cascode
op-amp is utilized for the second integrator.
Fig. 6. Schematic diagram of the first integrator.
Fig. 7. Schematic diagram of the second integrator.
3. 4-Bit Asynchronouis SAR ADC
A 4-bit asynchronous SAR ADC is used for the quantizer [14]. The SAR ADC is composed of a binary weighted capacitive digital-to-analog converter
(CDAC), a comparator, and a control logic as shown in Fig. 8. The SC passive summer in front of the quantizer is embedded at the CDAC. By sampling
the two inputs, V$_{\mathrm{INP}}$-V$_{\mathrm{INN}}$ and V$_{\mathrm{2P}}$-V$_{\mathrm{2N}}$,
into the same number of unit capacitors (8C), the same gain coefficients for the both
signal paths are achieved with a signal attenuation factor of 1 / 2. Since the input
common-mode voltage of the comparator is lower than V$_{\mathrm{DD}}$ / 2, a PMOS
input latched comparator illustrated in Fig. 9 is employed.
IV. MEASUREMENT RESULTS
The proposed delta-sigma ADC is implemented in a 28~nm CMOS process. The active die
area is 0.095 mm$^{2}$as shown in Fig. 10. It operates at a clock frequency of 512 kHz with an OSR of 256. It consumes 12.3
${\mu}$W with 0.8 V/0.85 V supply voltages. The power breakdown is given in Fig. 11.
The measured DR of the prototype ADC is 97.7 dB when input is shorted. It shows maximum
SNDR and SNR of 94.8 dB and 95.6 dB, respectively, at 150 Hz, -1~dBFS sinusoidal input.
Measured output spectrum is plotted in Fig. 12. Fig. 13 shows measured output spectrum with DWA turned on and off. It shows that capacitor
mismatches of CDAC degrades SNDR by 13.0~dB. Fig. 14 illustrates effect of CHS. When CHS is not used, SNDR is degraded to 82.1 dB due
to flicker noise of the first integrator. Fig. 15 shows the measured SNR and SNDR versus the input signal amplitude. Fig. 16 shows measured SFDR and SNDR versus the analog supply voltage. It suggests that the
performance is unaffected by the variation of the analog supply voltage from 0.8 to
1.1 V.
Fig. 8. Schematic diagram of the 4-bit asynchronous SAR ADC.
Fig. 9. Schematic diagram of PMOS input latched comparator.
Fig. 10. Die-photograph and chip layout of the proposed ADC.
Fig. 11. Power breakdown of the proposed modulator.
Fig. 12. Measured output spectrum.
Fig. 13. Measured output spectrum with DWA turned on (blue line) and off (red line).
Fig. 14. Measured output spectrum with CHS turned on (blue line) and off (red line).
Fig. 15. Measured SNR/SNDR versus input amplitude.
Fig. 16. Measured SNDR/SFDR versus analog supply voltage.
Table 1. summarizes the measured performance of the proposed ADC and compares it with the previous high-resolution and low bandwidth ADCs.
|
|
IEICE’19
[2]
|
VLSI’20 [15]
|
TCASII’21 [7]
|
TCASII’22 [16]
|
JSSC’23
[17]
|
This work
|
|
Architecture
|
DT
|
VCO
|
DT
|
CT
|
DT
|
DT
|
|
Process [nm]
|
180
|
65
|
110
|
180
|
55
|
28
|
|
FCLK [kHz]
|
1024
|
32
|
512
|
64
|
250
|
512
|
|
BW [kHz]
|
2
|
0.5
|
2
|
0.25
|
1
|
1
|
|
Analog Supply [V]
|
1.8
|
1.2
|
1.5
|
1.8
|
1.2
|
0.8
|
|
Digital Supply [V]
|
1.65
|
0.7
|
1.5
|
1.8
|
1.2
|
0.85
|
|
Power [μW]
|
63
|
3.2
|
62.43
|
2.16
|
2.87
|
12.3
|
|
DR [dB]
|
101
|
94.2
|
96.3
|
81.4
|
96.9
|
97.7
|
|
SNR [dB]
|
98.2
|
-
|
94
|
80.1
|
96.2
|
95.6
|
|
SNDR [dB]
|
97.1
|
88.1
|
93.9
|
78.4
|
94.0
|
94.8
|
|
Area [mm2]
|
0.095
|
0.08
|
0.165
|
0.29
|
0.136
|
0.095
|
|
*FoMS [dB]
|
176
|
176.1
|
171
|
162
|
182.3
|
176.8
|
*FoM
S = DR + 10∙log
10(BW/Power)
V. CONCLUSIONS
This paper presents a second order DT delta-sigma modulator. The proposed ADC adopts
a modified FF structure with delayed feedback for sufficient timing margin of the
loop filter. A Class-AB op-amp with floating class-AB control is employed at the first
integrator to achieve fast slewing with low static current. It is fabricated in a
28 nm CMOS process and achieves a DR of 97.7 dB and peak SNDR of 94.8 dB in a 1 kHz
signal BW while consuming 12.3 ${\mu}$W.
ACKNOWLEDGMENTS
This work was supported in part by the Technology Innovation Program (Development
of Ultra Low Power High Resolution Analog IP Module for Healthcare Sensors) funded
by the Ministry of Trade, Industry & Energy (MOTIE, South Korea) under Grant 20016379;
in part by Korea Institute for Advancement of Technology (KIAT) grant funded by the
Korea Government (MOTIE) under Grant P0017011; in part by the National Research Foundation
(NRF), under project BK21 FOUR; The EDA tool was supported by the IC Design Education
Center (IDEC), Korea
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Byeong-Ho Yu received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2022, where he is currently pursuing the M.S. degree. Mr. Yu is a
recipient of a scholarship sponsored by Samsung electronics. His current research
interests include low-power and high-speed CMOS data converters.
Jun-Ho Boo received the B.S. and Ph.D. degrees in electronic engi-neering from
Sogang University, Seoul, Korea, in 2017 and 2023 respectively, where he is a post-doctoral
researcher. His current research interests include analog and mixed-signal circuits,
data converters, and sensor interfaces.
Jae-Geun Lim received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2019, where he is currently pursuing the Ph.D. degree. Mr. Lim is
a recipient of a scholarship sponsored by Samsung electronics. His current research
interests include low-power and high-speed analog-to-digital converter.
Hyoung-Jung Kim received the B.S. degree in electronic engineering from Sogang
University, Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree.
Mr. Kim is a recipient of a scholarship sponsored by Samsung electronics. His current
interests are in the design of low-power and high-speed analog-to-digital converter.
Jae-Hyuk Lee received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree. Mr. Lee is
a recipient of a scholarship sponsored by Samsung electronics. His current interests
are in the design of high-speed, high-resolution CMOS data converters, and very high-speed
mixed-mode integrated systems.
Gil-Cho Ahn received the B.S. and M.S. degrees in electronic engi-neering from
Sogang University, Seoul, Korea, in 1994 and 1996, respectively, and the Ph.D. degree
in electrical engineering from Oregon State University, Corvallis, in 2005. From 1996
to 2001, he was a Design Engineer at Samsung Electronics, Kiheung, Korea, working
on mixed analog-digital integrated circuits. From 2005 to 2008, he was with Broadcom
Corporation, Irvine, CA, working on AFE for digital TV. Currently, he is a Professor
in the Department of Electronic Engineering, Sogang University. His research interests
include high-speed, high-resolution data converters and low-voltage, low-power mixed-signal
circuits design.