YuByeongHo^{1}
BooJunHo^{1}
LimJaeGeun^{1}
KimHyoungJung^{1}
LeeJaeHyuk^{1}
AhnGilCho^{1}

(Department of Electronic Engineering, Sogang University, Seoul 04107, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Analogtodigital converter (ADC), classAB opamp, deltasigma modulator, feedforward (FF), successive approximation register (SAR)
I. INTRODUCTION
Expansion of batterypowered portable devices has prompted the need to reduce power
consumption of deltasigma analogtodigital converters (ADCs), which have been widely
used in mobile sensor interfaces due to their high resolution and power efficiency
achieved by noise shaping and oversampling. Using input feedforward (FF) ^{[1]} is a widely used approach to reduce power consumption of the deltasigma ADC. This
approach makes the loop filter address quantization noise only. Consequently, the
requirement for the analog circuitry is relaxed, resulting in a reduction in power
consumption. Furthermore, in ^{[2]}, the removal of the internal FF path reduces the current consumed by the first integrator,
as it no longer drives the sampling capacitor of the quantizer. Despite these architectural
efforts, reducing the power consumption of the modulator remains challenging. The
main bottleneck lies in the fact that the opamp of the loop filter must drive large
capacitors that satisfy the kT / C noise requirement within a given clock period.
The ClassAB opamp is one of the suitable solutions to deal with this difficulty.
It consumes dynamic current through pushpull operation during slewing and wastes
only a small amount of quiescent current during settling. Therefore, the average current
is reduced. This property makes it wellsuited for low power applications ^{[3}^{6]}.
This work proposes a discretetime (DT) 2$^{\mathrm{nd}}$ order deltasigma modulator
achieving a dynamic range (DR) of 97.7 dB at a 1 kHz bandwidth while consuming a power
of 12.3 ${\mu}$W. The architecture of the modulator is based on a previously proposed
work, which employs modified FF structure with delayed feedback ^{[7]}. The proposed ADC adopts a classAB opamp ^{[8]} for the first integrator to reduce average current and enhance the slew rate. The
architecture of the prototype ADC is discussed in Section II. Detailed implementation
of the opamp and the ADC is discussed in Section III. The measured results of the
prototype ADC are summarized in Section IV. Finally, a brief conclusion is discussed
in Section V.
II. ARCHITECTURE
Fig. 1 illustrates the zdomain block diagram of the proposed ADC. It consists of two integrators,
a 4bit asynchronous type successive approximation register (SAR) ADC that incorporates
a passive switched capacitor (SC) adder, as well as digital circuitry including a
clock generator, a dynamic weight averaging (DWA), and a binarytothermometer decoder.
A delay of one clock period is inserted in the feedback path to relax the timing constraints
of the modulator ^{[7]}. Output of the modulator, Do(z), and input of the first integrator, L(z), is given
by
where U(z) and Q(z) indicate the input of the modulator and quantization noise, respectively.
It can be observed that the delay in the feedback path introduces nonideal characteristics
even though the noise transfer function, NTF(z), is not affect. Firstly, the signal
transfer function, STF(z), becomes frequency dependent as depicted in (2). Secondly, (4) shows that the loop filter processes a thirdorder shaped input, whereas that of
a conventional FF modulator only handles quantization noise. However, these nonideal
properties can be suppressed by employing a decimation filter and an antialiasing
filter (AAF) with a sufficient oversampling ratio (OSR). The outofband signal amplified
by the STF(z), which is folded back to in band after the downsampling, can be effectively
mitigated using a loworder decimation filter if the OSR is large enough. Moreover,
the AAF allows the first integrator to deal with only a negligible amount of the outofband
input.
Fig. 1. Block diagram of the proposed modulator.
III. CIRCUIT IMPLEMENTATION
1. Fully Differential Class AB OpAmp
To efficiently drive the 6 pF feedback capacitor of the first integrator and 500 fF
sampling capacitor of the second integrator, which are chosen to meet the kT / C noise
requirement, a classAB opamp is utilized for the first integrator. The classAB
opamp charges or discharges the loading capacitor by pushpull operation during slewing
while spending optimized current. During the settling period, it consumes only a small
amount of quiescent current. Consequently, employing the classAB opamp can result
in reduced power consumption compared to the classA opamp, which draws static current
during both the slewing and settling periods. To implement classAB operation, this
work uses the floating classAB control ^{[8]}.
Fig. 2 illustrates a railtorail output stage with a floating classAB control. The floating
classAB control transistors M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$ are biased by
stacked diode connected transistors, M$_{\mathrm{B1}}$M$_{\mathrm{B4}}$. When inphase
current I$_{\mathrm{IN1}}$ and I$_{\mathrm{IN2}}$ are pushed to control transistors
M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$, the V$_{\mathrm{SP}}$ and V$_{\mathrm{SN}}$
voltages get raised while the difference between these two voltages remains constant.
So that the loaded capacitor of the output node is discharged. Conversely, when I$_{\mathrm{IN1}}$
and I$_{\mathrm{IN2}}$ are pulled from M$_{\mathrm{C1}}$ and M$_{\mathrm{C2}}$, the
V$_{\mathrm{SP}}$ and V$_{\mathrm{SN}}$ voltages go down, and the loaded capacitor
is charged. This pushpull operation continues until the drain current of M$_{\mathrm{C1}}$
matches I$_{1}$.
Fig. 3 is a schematic diagram of the twostage opamp used in the first integrator. The
first stage adopts foldedcascode topology to achieve sufficient DC gain. The input
PMOS devices M$_{1}$ and M$_{2}$, operate at subthreshold region for better noise
performance ^{[12]}. The floating classAB control is implemented using the transistors M$_{9}$M$_{12}$.
The noise and the offset of the classAB control transistors can be simply mitigated
by shifting these transistors into the summing circuit of the first stage opamp ^{[8]}. Then, noise and offset of the opamp are mainly determined by the first stage opamp.
M$_{21}$M$_{28}$form inverting amplifiers for commonmode feedback (CMFB) operation
which will be discussed in subsequent discussion.
Typically, a fully differential multistage opamp employs CMFB at each stage ^{[9}^{11]}. However, using the floating classAB control scheme with such CMFB is not eligible
as the output stage consist of pushpull transistors operating in a pseudo differential
manner. In this design, a single CMFB with a global feedback loop is utilized, which
senses the output common at the classAB second stage output and controls current
source of the classA first stage ^{[3]}. As depicted in Fig. 4, the global loop CMFB comprises two commonmode control paths that generate the current
control voltages for the upper and lower sides (V$_{\mathrm{CMFBU}}$ and V$_{\mathrm{CMFBL}}$).
Each path consists of a SC CMFB circuit, an inverting amplifier, and floating current
sources for upper and lower side commonmode control.
The SC CMFBs sense the output common of the opamp and generate control voltages V$_{\mathrm{CML}}$
and V$_{\mathrm{CMU}}$, which move in the same direction as the output common mode
with a level shifting operation. Then, the commonmode control voltages V$_{\mathrm{CMFBL}}$
and V$_{\mathrm{CMFBU}}$, are generated by inverting V$_{\mathrm{CML}}$ and V$_{\mathrm{CMU}}$
for negative feedback. Subsequently, V$_{\mathrm{CMFBL}}$ and V$_{\mathrm{CMFBU}}$
adjust the output common by controlling floating current sources.
A schematic diagram of the inverting amplifier is shown in Fig. 5. The inverting amplifier for the NMOS current sources consists of M$_{\mathrm{N1}}$,
M$_{\mathrm{N2}}$, and M$_{\mathrm{N3}}$, while the inverting amplifier for the PMOS
current sources comprises M$_{\mathrm{P1}}$, M$_{\mathrm{P2}}$, and M$_{\mathrm{P3}}$.
If the output impedance of the current source (I$_{\mathrm{N}}$, I$_{\mathrm{P}}$)
is sufficiently large, gain of the amplifier, A$_{CMFB}$ is given by
where g$_{M}$$_{\mathrm{N1,}}$$_{M}$$_{\mathrm{P1}}$represents the transconductance
of M$_{\mathrm{N1}}$, and M$_{\mathrm{P1}}$, while g$_{M}$$_{\mathrm{N2}}$, $_{M}$$_{\mathrm{P2}}$
indicates the transconductance of M$_{\mathrm{N2}}$and M$_{\mathrm{P2}}$. Eq. (5) suggests that the settling speed and stability of the output common mode can be adjusted
by controlling the transconductance ratio. In this work, a gain of  1 / 3 is chosen
to ensure the stable convergence of the output common mode.
Fig. 2. Schematic diagram of the railtorail output stage with a floating classAB control.
Fig. 3. Schematic diagram of the twostage opamp used in the first integrator.
Fig. 4. Block diagram of the global loop CMFB.
Fig. 5. Inverting amplifier of the global loop CMFB.
2. Loop Filter
Fig. 6 illustrates the first integrator of the loop filter. Bootstrapping switch is incorporated
to enhance linearity of the sampling network. In order to mitigate the 1/f noise and
offset, chopper stabilization (CHS) ^{[13]} is employed. The classAB opamp discussed in the previous section is adopted to
improve power efficiency.
The transfer function of the second integrator, (2  z$^{1}$) / (1  z$^{1}$), is
implemented as shown in Fig. 7. It samples the first integrator output on the C$_{\mathrm{S2}}$ during the ${\phi}$
$_{\mathbf{2}}$ phase. In the following ${\phi}$ $_{\mathbf{1}}$ phase, the output
of the first integrator is connected to the C$_{\mathrm{S2A}}$ as well as the C$_{\mathrm{S2}}$
and integrated without delay.
Given that the integrator only needs to drive a feedback capacitor C$_{\mathrm{F2}}$,
which is 250 fF, and 80 fF sampling capacitor of the quantizer, using a classAB opamp
may not be highly efficient. This is due to the fact that employing a classAB opamp
would require additional biasing branches and control circuits. Hence, a simple foldedcascode
opamp is utilized for the second integrator.
Fig. 6. Schematic diagram of the first integrator.
Fig. 7. Schematic diagram of the second integrator.
3. 4Bit Asynchronouis SAR ADC
A 4bit asynchronous SAR ADC is used for the quantizer ^{[14]}. The SAR ADC is composed of a binary weighted capacitive digitaltoanalog converter
(CDAC), a comparator, and a control logic as shown in Fig. 8. The SC passive summer in front of the quantizer is embedded at the CDAC. By sampling
the two inputs, V$_{\mathrm{INP}}$V$_{\mathrm{INN}}$ and V$_{\mathrm{2P}}$V$_{\mathrm{2N}}$,
into the same number of unit capacitors (8C), the same gain coefficients for the both
signal paths are achieved with a signal attenuation factor of 1 / 2. Since the input
commonmode voltage of the comparator is lower than V$_{\mathrm{DD}}$ / 2, a PMOS
input latched comparator illustrated in Fig. 9 is employed.
IV. MEASUREMENT RESULTS
The proposed deltasigma ADC is implemented in a 28~nm CMOS process. The active die
area is 0.095 mm$^{2}$as shown in Fig. 10. It operates at a clock frequency of 512 kHz with an OSR of 256. It consumes 12.3
${\mu}$W with 0.8 V/0.85 V supply voltages. The power breakdown is given in Fig. 11.
The measured DR of the prototype ADC is 97.7 dB when input is shorted. It shows maximum
SNDR and SNR of 94.8 dB and 95.6 dB, respectively, at 150 Hz, 1~dBFS sinusoidal input.
Measured output spectrum is plotted in Fig. 12. Fig. 13 shows measured output spectrum with DWA turned on and off. It shows that capacitor
mismatches of CDAC degrades SNDR by 13.0~dB. Fig. 14 illustrates effect of CHS. When CHS is not used, SNDR is degraded to 82.1 dB due
to flicker noise of the first integrator. Fig. 15 shows the measured SNR and SNDR versus the input signal amplitude. Fig. 16 shows measured SFDR and SNDR versus the analog supply voltage. It suggests that the
performance is unaffected by the variation of the analog supply voltage from 0.8 to
1.1 V.
Fig. 8. Schematic diagram of the 4bit asynchronous SAR ADC.
Fig. 9. Schematic diagram of PMOS input latched comparator.
Fig. 10. Diephotograph and chip layout of the proposed ADC.
Fig. 11. Power breakdown of the proposed modulator.
Fig. 12. Measured output spectrum.
Fig. 13. Measured output spectrum with DWA turned on (blue line) and off (red line).
Fig. 14. Measured output spectrum with CHS turned on (blue line) and off (red line).
Fig. 15. Measured SNR/SNDR versus input amplitude.
Fig. 16. Measured SNDR/SFDR versus analog supply voltage.
Table 1. summarizes the measured performance of the proposed ADC and compares it with the previous highresolution and low bandwidth ADCs.

IEICE’19
^{[2]}

VLSI’20 ^{[15]}

TCASII’21 ^{[7]}

TCASII’22 ^{[16]}

JSSC’23
^{[17]}

This work

Architecture

DT

VCO

DT

CT

DT

DT

Process [nm]

180

65

110

180

55

28

F_{CLK }[kHz]

1024

32

512

64

250

512

BW [kHz]

2

0.5

2

0.25

1

1

Analog Supply [V]

1.8

1.2

1.5

1.8

1.2

0.8

Digital Supply [V]

1.65

0.7

1.5

1.8

1.2

0.85

Power [μW]

63

3.2

62.43

2.16

2.87

12.3

DR [dB]

101

94.2

96.3

81.4

96.9

97.7

SNR [dB]

98.2



94

80.1

96.2

95.6

SNDR [dB]

97.1

88.1

93.9

78.4

94.0

94.8

Area [mm^{2}]

0.095

0.08

0.165

0.29

0.136

0.095

*FoM_{S} [dB]

176

176.1

171

162

182.3

176.8

*FoM
_{S }= DR + 10∙log
_{10}(BW/Power)
V. CONCLUSIONS
This paper presents a second order DT deltasigma modulator. The proposed ADC adopts
a modified FF structure with delayed feedback for sufficient timing margin of the
loop filter. A ClassAB opamp with floating classAB control is employed at the first
integrator to achieve fast slewing with low static current. It is fabricated in a
28 nm CMOS process and achieves a DR of 97.7 dB and peak SNDR of 94.8 dB in a 1 kHz
signal BW while consuming 12.3 ${\mu}$W.
ACKNOWLEDGMENTS
This work was supported in part by Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Ministry of Trade, Industry & Energy (MOTIE, South Korea) under Grant 20016379, Development of Ultra Low Power High Resolution Analog IP Module for Healthcare Sensors; in part by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) under Grant P0017011; in part by the National Research Foundation (NRF), under project BK21 FOUR; The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
References
J. Silva, U. Moon, J. Steensguqrd, and G. C. Temes, “Wide band low distortion deltasigma
ADC topology,” IEE Electron. Lett., vol. 37, no.12, pp. 737738, Jun. 2001.
K. Cho, Y. Kwak, H. Kim, and G. Ahn, “A 101dB dynamic range, 2kHz bandwidth deltasigma
modulator with a modified feedforward architecture,” IEICE Electron. Exp., vol. 15,
no. 21, 2018, Art. no. 20180848.
Y. J. Kim, H. C. Choi, G. C. Ahn and S. H. Lee, "A 12 bit 50 MS/s CMOS Nyquist
A/D Converter With a Fully Differential ClassAB Switched OpAmp," in IEEE Journal
of SolidState Circuits, vol. 45, no. 3, pp. 620628, March 2010.
M. S. Akter, R. Sehgal, F. van der Goes, K. A. A. Makinwa and K. Bult, "A 66dB SNDR
Pipelined SplitADC in 40nm CMOS Using a ClassAB Residue Amplifier," in IEEE Journal
of SolidState Circuits, vol. 53, no. 10, pp. 29392950, Oct. 2018.
J. H. Boo et al., "A SingleTrim Switched Capacitor CMOS Bandgap Reference With a
3σ Inaccuracy of +0.02%, −0.12% for BatteryMonitoring Applications," in IEEE Journal
of SolidState Circuits, vol. 56, no. 4, pp. 11971206, April 2021.
V. Shirmohammadli, A. Saberkari, H. MartinezGarcia and E. AlarcónCot, "Low power
outputcapacitorless classAB CMOS LDO regulator," 2017 IEEE International Symposium
on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 14.
J. Han, K. Cho, H. Kim, J. Boo, J. Kim, and G. Ahn, “A 96dB dynamic range 2kHz bandwidth
2nd order deltasigma modulator using modified feedforward architecture with delayed
feedback,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 5, pp. 16451649,
May 2021.
R. Hogervorst, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, "A compact powerefficient
3 V CMOS railtorail input/output operational amplifier for VLSI cell libraries,"
in IEEE Journal of SolidState Circuits, vol. 29, no. 12, pp. 15051513, Dec. 1994.
B. Park, C. Han and N. Maghari, "Correlated DualLoop Sturdy MASH CT ΔΣ ADC with Indirect
Signal Feedforward," 2021 IEEE Asian SolidState Circuits Conference (ASSCC), Busan,
Korea, Republic of, 2021, pp. 13.
J. S. Park, et.al., "A 12b 100MS/s ThreeStep Hybrid Pipeline ADC Based on TimeInterleaved
SAR ADCs," J. Semicoductor Technology and Science (JSTS), vol. 14, no. 2, pp. 189197,
Apr. 2014.
T. An, et.al., "A Twochannel 10b 160 MS/s 28 nm CMOS Asynchronous PipelinedSAR
ADC with Low Channel Mismatch," J. Semicoductor Technology and Science (JSTS), vol.
17, no. 5, pp. 636647, Oct. 2017.
M. Maruyama, S. Taguchi, M. Yamanoue and K. Iizuka, "A 24bit multifunctional sensor
analog front end employing low noise biasing technique with 8.2nV/√Hz input referred
noise," 2015 IEEE Asian SolidState Circuits Conference (ASSCC), Xiamen, China, 2015,
pp. 14.
C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of opamp
imperfections: Autozeroing, correlated double sampling, and chopper stabilization,”
Proc. IEEE, vol. 84, no. 11, pp. 15841614, Nov. 1996.
J. S. Kim, T. I. Kwon, G. C. Ahn, Y. G. Kim and J. K. Kwon, "A ΔΣ ADC using 4bit
SAR type quantizer for audio applications," 2011 International SoC Design Conference,
Jeju, Korea (South), 2011, pp. 7375.
J. Huang and P. P. Mercier, "A −105dB THD 88dBSNDR VCOBased Sensor FrontEnd Enabled
by BackgroundCalibrated Differential Pulse Code Modulation," 2020 IEEE Symposium
on VLSI Circuits, Honolulu, HI, USA, 2020, pp. 12.
J. Kim, Q. Duan, J. Choi, C. Song and J. Roh, "A 2.16μW LowPower ContinuousTime
DeltaSigma Modulator With ImprovedLinearity Gm for Wearable ECG Application," in
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp.
42234227, Nov. 2022.
L. Meng et al., "A 1.2V 2.87μ W 94.0dB SNDR DiscreteTime 20 MASH DeltaSigma
ADC," in IEEE Journal of SolidState Circuits, vol. 58, no. 6, pp. 16361645, June
2023.
ByeongHo Yu received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2022, where he is currently pursuing the M.S. degree. Mr. Yu is a
recipient of a scholarship sponsored by Samsung electronics. His current research
interests include lowpower and highspeed CMOS data converters.
JunHo Boo received the B.S. and Ph.D. degrees in electronic engineering from
Sogang University, Seoul, Korea, in 2017 and 2023 respectively, where he is a postdoctoral
researcher. His current research interests include analog and mixedsignal circuits,
data converters, and sensor interfaces.
JaeGeun Lim received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2019, where he is currently pursuing the Ph.D. degree. Mr. Lim is
a recipient of a scholarship sponsored by Samsung electronics. His current research
interests include lowpower and highspeed analogtodigital converter.
HyoungJung Kim received the B.S. degree in electronic engineering from Sogang
University, Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree.
Mr. Kim is a recipient of a scholarship sponsored by Samsung electronics. His current
interests are in the design of lowpower and highspeed analogtodigital converter.
JaeHyuk Lee received the B.S. degree in electronic engineering from Sogang University,
Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree. Mr. Lee is
a recipient of a scholarship sponsored by Samsung electronics. His current interests
are in the design of highspeed, highresolution CMOS data converters, and very highspeed
mixedmode integrated systems.
GilCho Ahn received the B.S. and M.S. degrees in electronic engineering from
Sogang University, Seoul, Korea, in 1994 and 1996, respectively, and the Ph.D. degree
in electrical engineering from Oregon State University, Corvallis, in 2005. From 1996
to 2001, he was a Design Engineer at Samsung Electronics, Kiheung, Korea, working
on mixed analogdigital integrated circuits. From 2005 to 2008, he was with Broadcom
Corporation, Irvine, CA, working on AFE for digital TV. Currently, he is a Professor
in the Department of Electronic Engineering, Sogang University. His research interests
include highspeed, highresolution data converters and lowvoltage, lowpower mixedsignal
circuits design.